A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Abstract

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

1. Introduction

Future generation of communication systems will operate at multigigabit-per-second data rates on highly dispersive channels [1, 2]. In commercial applications, the digital receiver is often implemented as a monolithic chip in CMOS technology [1]. Maximum clock frequency of state-of-the-art complex digital signal processors in 28 nm CMOS technology is limited to frequencies lower than 1 GHz. Therefore, in order to achieve multigigabit-per-second data rates, parallel processing techniques are required [1].

Maximum likelihood sequence detection (MLSD) and decision feedback equalization (DFE) are two efficient techniques used to compensate the high ISI introduced by such channels as the ones described in [3]. The complexity of the former grows exponentially with the channel memory, regardless of whether parallel processing is used or not. As for the latter, although the complexity of serial implementations grows linearly with channel memory, all presently known parallel processing implementations require that the bottleneck created by the feedback loop be broken using techniques like the ones proposed by [4–6], whose complexity again grows exponentially with the channel memory.

Some algorithms to deal with the drawbacks of the DFE in high-speed applications and parallel processing have been proposed by [4–12]. For example, parallel DFE architectures based on look-ahead pipelined multiplexer loops have been introduced in [6, 7]. These architectures can mitigate the speed limitation of feedback loops by using nested multiplexer loops where the implementation is reported in [10]. Some further improvements to these schemes have been proposed in [8, 9]. However, the implementation complexity of DFE parallel architectures based on look-ahead pipelined multiplexer loops still increases exponentially with the number of feedback taps. Recent works [11, 12] present the concurrent look-ahead technique for high-speed data rate. This scheme reduces the hardware complexity in comparison with a look-ahead pipelined multiplexer loops technique, but the decision loop is not broken.

Iterative interference cancellation and turbo equalization have received increasing attention in recent years [13]. For example, iterative cancellation is proposed in [14–17] where nonlinear equalizers for ISI channels are introduced. This technique uses an iterative algorithm to successively cancel ISI from a block of received data. The algorithm generates symbol decisions whose reliability increases monotonically with each iteration. According to these authors, so far these techniques have not been applied to create efficient pipelined and parallel-processing implementations of equalizer structures for ultra-high-speed applications despite its interesting characteristics. Therefore, the application of both DFE and MLSD is limited to moderate ISI channels. As a consequence, there is a need for reduced-complexity receivers which can operate efficiently on channels with large ISI.

A preliminary study of a new low-complexity iterative equalization architecture for high-speed receivers is introduced in [18]. The decision feedforward equalizer (DFFE) allows to obtain similar performance to DFE with a parallelizable architecture, whose complexity increases only quadratically with the channel memory. For channels with large ISI this results in a dramatic complexity reduction if compared with DFE. The central idea behind DFFE is the iteration of tentative decisions to improve the accuracy of the ISI estimation. We would like to highlight that tentative decisions have been used in the past to cancel FEXT interference [19].

Finally, the error probability in the DFE has been widely discussed in the literature with numerous authors who develop different methods to estimate the error probability in DFE [20–24].

In this work, we explain the concept of DFFE and its implementation complexity to parallel architectures. Moreover, we propose a theoretical approximation for the error probability in each iteration, where it is easy to appreciate that when the number of iteration increases the error probability in the DFFE tends to approach the DFE.

This paper is organized as follows. The concept of DFFE is explained in Section 2. In Section 3 the performance evaluation is researched. Section 4 analyzes parallel architectures for DFFE and implementation complexity. Finally, conclusions are drawn in Section 5.

2. Decision Feedforward Equalization (DFFE)

To begin with, we will explain the concept of DFFE. For simplicity, we only consider a dispersive channel with postcursor ISI. Our results can be generalized to channels with both pre- and postcursor ISIs by combining the DFFE with a feedforward equalizer [3]. Let 𝑦_𝑛, 𝑎_𝑛^(𝑖), and 𝐿 be the DFFE input sample, the tentative decision at the 𝑖th iteration, and the memory of the channel, respectively. At the first iteration, 𝑖=0, we get the first tentative decision without any cancellation of interference: 𝑎_𝑛⁽⁰⁾=𝒬𝑦_𝑛, (1) where 𝒬(⋅) is the slicer function. This tentative decision can be then used to cancel the postcursor ISI introduced by the first past symbol and thus to improve the accuracy of the detection. By using proper time delays, we can obtain the tentative decision at the second iteration as follows: 𝑎_𝑛⁽¹⁾=𝒬𝑦_𝑛−𝑓₁𝑎⁽⁰⁾_𝑛−1, (2) where 𝑓_𝑘(⋅) with 0<𝑘<𝐿 denotes the partial postcursor ISI caused by the past 𝑘 symbols. This process is repeated at least until 𝐿 consecutive tentative decisions are available. At this point, a final decision can be obtained from 𝑎_𝑛=𝑎_𝑛^(𝐿)=𝒬𝑦_𝑛−𝑓_𝐿𝑎^(𝐿−1)_𝑛−1,…,𝑎⁽⁰⁾_𝑛−𝐿, (3) where 𝑓_𝐿(⋅) is the total postcursor ISI of the channel. Based on an information theory metric [25], in this work we show that the reliability of the tentative decision 𝑎_𝑛^(𝑖) improves as the number of iteration 𝑖 grows. In this way, both the accuracy of the interference estimate and the performance of the DFFE are improved with the number of iterations. Numerical results derived from computer simulations demonstrate that the DFFE can achieve performance similar to the DFE on highly dispersive channels. Furthermore, since tentative decisions are used instead of final decisions to estimate the postcursor ISI, it is possible to implement the DFFE in a feedforward way, which leads to a direct parallel implementation. We show that the computational complexity of the DFFE grows quadratically with 𝐿. This results in a drastic complexity reduction in comparison to parallel architectures for the DFE where the computational load grows exponentially with 𝐿. This favorable tradeoff between performance and complexity makes the DFFE an excellent alternative for implementing high-speed receivers in transmissions over highly dispersive channels.

As we expressed above, the iterative use of tentative decisions to estimate the postcursor ISI is the key to DFFE. In the following section, we use the mutual information [25] to show how the iterations impact the reliability of the tentative decisions. In addition, we study the DFFE performance in transmissions over channels with high memory.

2.1. Architecture of DFFE

The received sample is given by 𝑦_𝑛=𝑎_𝑛+^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+𝑧_𝑛, (4) where 𝑑_𝑘 with 𝑘=1,…,𝐿 is the postcursor ISI tap, 𝑎_𝑛 is the transmitted symbol (e.g., 𝑎_𝑛∈{±1}), and 𝑧_𝑛 is white Gaussian noise with power 𝜎². Assuming that the channel is known at the receiver (i.e., perfect channel estimation), the detected symbol provided by the DFFE at instant 𝑛 given by (3) can be rewritten as 𝑎_𝑛=𝑎_𝑛^(𝑅−1)=𝒬𝑦_𝑛−^𝐿_𝑘=1𝑎^{(𝑅−1−𝑘)}_𝑛−𝑘𝑑_𝑘, (5) where 𝑅 with 𝑅>𝐿 is the total number of iterations. The first 𝐿 tentative decisions are calculated iteratively as follows: 𝑎_𝑛^(𝑖)=𝒬𝑦_𝑛−^𝑖_𝑘=1𝑎^{(𝑖−𝑘)}_𝑛−𝑘𝑑_𝑘,1≤𝑖<𝐿, (6) with 𝑎_𝑛⁽⁰⁾=𝒬(𝑦_𝑛) for 𝑖=0.

Figure 1 shows the architecture of the DFFE for a channel with memory 𝐿=3 and 𝑅=5. Note that the final decision 𝑎_𝑛=𝑎_𝑛⁽⁴⁾ uses past tentative decisions to estimate the postcursor interference, and not previous final decisions as in the DFE. As we will show later, this fact allows the direct parallel implementation of the DFFE.

Figure 1 

Example of a 3-tap DFFE (𝐿=3) with 𝑅=5. (a) Note that the latency between the input signal and the decision is 𝑅−1. (b) The red dashed line denotes the critical path (see Section 4.4).

2.2. Reliability of the Tentative Decisions

Next, we analyze the mutual information between the transmit symbol 𝑎_𝑛 and the tentative decision at the 𝑖th iteration, 𝑎_𝑛^(𝑖), defined by 𝐼𝑎_𝑛,𝑎_𝑛^(𝑖)=𝐻𝑎_𝑛−𝐻𝑎_𝑛∣𝑎_𝑛^(𝑖), (7) where 𝐻(⋅) and 𝐻(⋅∣⋅) denote entropy and conditional entropy, respectively [25]. Note that 𝐼(𝑎_𝑛,𝑎_𝑛^(𝑖)) is the information on 𝑎_𝑛 contained in 𝑎_𝑛^(𝑖). For example, for binary transmit symbols, 𝐼(𝑎_𝑛,𝑎_𝑛^(𝑖))=1 indicates that no error occurs in the tentative decisions (i.e., Pr{𝑎_𝑛^(𝑖)=𝑎_𝑛}=1). On the other hand, in the presence of a high error rate in the tentative decisions (i.e., Pr{𝑎_𝑛^(𝑖)≠𝑎_𝑛}=1), the mutual information gets 𝐼(𝑎_𝑛,𝑎_𝑛^(𝑖))=0. Thus, it can be concluded that the mutual information (7) provides a measure of the reliability of the tentative decision 𝑎_𝑛^(𝑖).

2.3. Numerical Results

Figure 2(a) depicts the mutual information versus the signal-to-noise ratio (SNR), defined as SNR=𝐸{|𝑎_𝑛|²}/𝜎². We consider 𝑎_𝑛∈{±1} and a postcursor ISI channel modeled as 𝑑_𝑘=𝛼^𝑘0<𝑘≤𝐿,0otherwise, (8) with 𝛼 being a positive number smaller than one. In Figure 2(a) we consider 𝛼=0.6 with 𝐿=10 and a DFFE with 𝑅=11. Notice that the mutual information grows as the SNR increases; in a limit case, note that 𝐼(𝑎_𝑛,𝑎_𝑛^(𝑅−1))=𝐼(𝑎_𝑛,𝑎_𝑛)→1 for SNR→∞. For a given value of SNR, note that the minimum mutual information (or reliability) is verified at the first iteration (𝑖=0). This can be understood from (1) in which it is observed that the first tentative decision is obtained directly from the received sample without any cancellation of interference. Nevertheless, although the reliability of 𝑎_𝑛⁽⁰⁾ is low, some information of the transmit symbol 𝑎_𝑛 is contained in 𝑎_𝑛⁽⁰⁾. More precisely, this fact is exploited in the second iteration (𝑖=1), in which it is observed that the reliability of 𝑎_𝑛⁽¹⁾ has been improved as a result of the partial cancellation of the postcursor ISI caused by 𝑎_𝑛⁽⁰⁾. This process is repeated in the following iterations until the last iteration 𝑖=𝑅−1 is reached. At this point, the DFFE is able to provide the final decision 𝑎_𝑛=𝑎_𝑛^(𝑅−1) with a high reliability.

(a)

(b)

Figure 2 

Reliability of the DFFE tentative decisions. (a) Mutual information versus SNR for 𝛼=0.6, 𝐿=10, and 𝑅=11. (b) Mutual information versus number of iterations for different postcursor channels with SNR=15dB.

Figure 2(b) shows the mutual information versus the number of iterations for several postcursor ISI channels with SNR=15dB. We use 𝛼=0.6, 0.82, and 0.92 with 𝐿=10, 30, and 60, respectively. In all cases, it can be observed that the reliability of the tentative decisions improves with the number of iterations. In particular, note that the reliability of the DFFE decisions at 𝑅>𝐿 tends to reach that of the DFE. This result suggests that the performances of the DFE and the DFFE with 𝑅>𝐿 iterations should be similar.

3. Performance Evaluation

From (4) and (5), the slicer input signal at the 𝑖th iteration, 𝑦_𝑛^(𝑖), can be expressed as 𝑦_𝑛^(𝑖)=𝑎_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+𝑧_𝑛𝑎,𝑖=0,_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘−∑^𝑖_𝑘=1𝑎^{(𝑖−𝑘)}_𝑛−𝑘𝑑_𝑘+𝑧_𝑛𝑎,0<𝑖<𝐿,_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘−∑^𝐿_𝑘=1𝑎^{(𝑖−𝑘)}_𝑛−𝑘𝑑_𝑘+𝑧_𝑛,𝑖≥𝐿. (9)

Let Ψ_𝑛^(𝑖) be the DFFE-state vector at the 𝑖th iteration defined by Ψ_𝑛^(𝑖)=𝑎_𝑛−1,𝑎_𝑛−2,…,𝑎_𝑛−𝐿𝑎,𝑖=0,_𝑛−1,𝑎_𝑛−2,…,𝑎_𝑛−𝐿,𝑎^(𝑖−1)_𝑛−1,𝑎^(𝑖−2)_𝑛−2,…,𝑎⁽⁰⁾_𝑛−𝑖𝑎,0<𝑖<𝐿,_𝑛−1,𝑎_𝑛−2,…,𝑎_𝑛−𝐿,𝑎^(𝑖−1)_𝑛−1,𝑎^(𝑖−2)_𝑛−2,….,𝑎⁽⁰⁾_𝑛−𝐿,𝑖≥𝐿. (10) Let 𝑁_𝑖 denote the dimension of the state vector Ψ_𝑛^(𝑖). Thus, observe that Ψ_𝑛^(𝑖)∈𝜓^(𝑖,0),𝜓^(𝑖,1),…,𝜓^{(𝑖,2𝑁𝑖−1)}, (11) where 𝜓^(𝑖,0)=(+1,+1,…,+1), 𝜓^(𝑖,1)=(+1,+1,…,−1),…, 𝜓^{(𝑖,2𝑁𝑖−1)}=(−1,−1,…,−1), are 𝑁_𝑖-dimensional vectors. The slicer input signal at the 𝑖th iteration given by (9) can be rewritten as 𝑦_𝑛^(𝑖)=𝑔𝑎_𝑛,Ψ_𝑛^(𝑖)+𝑧_𝑛, (12) where 𝑔𝑎_𝑛,Ψ_𝑛^(𝑖)=𝑎_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘𝑎,𝑖=0,_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘−∑^𝑖_𝑘=1𝑎^{(𝑖−𝑘)}_𝑛−𝑘𝑑_𝑘𝑎,0<𝑖<𝐿,_𝑛+∑^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘−∑^𝐿_𝑘=1𝑎^{(𝑖−𝑘)}_𝑛−𝑘𝑑_𝑘,𝑖≥𝐿. (13)

Then, the probability density function (pdf) given the transmit symbol 𝑎_𝑛 can be expressed as 𝑓_𝑦∣𝑎𝑦_𝑛^(𝑖)∣𝑎_𝑛=^{2𝑁𝑖−1}_𝑘=0𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,𝑘)𝑃𝜓^(𝑖,𝑘), (14) where 𝑃(𝜓^(𝑖,𝑘))=Pr{Ψ_𝑛^(𝑖)=𝜓^(𝑖,𝑘)} and 𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,𝑘)=1√𝑒2𝜋𝜎^{−(1/2𝜎2)(𝑦𝑛(𝑖)−𝑔(𝑎𝑛,𝜓(𝑖,𝑘)))2}. (15) The symbol error probability at the 𝑖th iteration is 𝑃_𝑒^(𝑖)=Pr𝑦_𝑛^(𝑖)<0∣𝑎_𝑛=+1Pr𝑎_𝑛𝑦=+1+Pr_𝑛^(𝑖)≥0∣𝑎_𝑛=−1Pr𝑎_𝑛=−1. (16) Note that Pr{𝑦_𝑛^(𝑖)<0∣𝑎_𝑛=+1} and Pr{𝑦_𝑛^(𝑖)≥0∣𝑎_𝑛=−1} can be computed by using the pdf given by (14).

3.1. Example

In the following equations we consider a postcursor channel with 𝐿=1 and 𝑑₁=1 (i.e., a duobinary channel). At the first iteration, we get Ψ_𝑛⁽⁰⁾=𝑎_𝑛−1,𝑔𝑎_𝑛,Ψ_𝑛⁽⁰⁾=𝑎_𝑛+𝑎_𝑛−1. (17)(18) Note that 𝑁_𝑖=1 and Ψ_𝑛⁽⁰⁾∈𝜓^(0,0),𝜓^(0,1) (19) with 𝜓^(0,0)=(+1) and 𝜓^(0,1)=(−1). The transmit symbols are assumed independent and identically distributed with Pr𝑎_𝑛=+1=Pr𝑎_𝑛=1=−12∀𝑛. (20) In this situation, from (17) and (19) note that 𝑃𝜓^(0,𝑘)=12,𝑘=0,1. (21) The error probability 𝑃_𝑒⁽⁰⁾ can be derived from (16) and 𝑓_𝑦∣𝑎𝑦_𝑛⁽⁰⁾∣𝑎_𝑛=12¹_𝑘=0𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛⁽⁰⁾∣𝑎_𝑛,𝜓^(0,𝑘). (22)

At the second iteration, we get Ψ_𝑛⁽¹⁾=𝑎_𝑛−1,𝑎⁽⁰⁾_𝑛−1,𝑔𝑎_𝑛,Ψ_𝑛⁽¹⁾=𝑎_𝑛+𝑎_𝑛−1−𝑎⁽⁰⁾_𝑛−1. (23)(24) In this case, notice that 𝑁_𝑖=2 and Ψ_𝑛⁽¹⁾∈𝜓^(1,0),𝜓^(1,1),𝜓^(1,2),𝜓^(1,3) (25) with 𝜓^(1,0)=(+1,+1), 𝜓^(1,1)=(+1,−1), 𝜓^(1,2)=(−1,+1), and 𝜓^(1,3)=(−1,−1). From (20) and (23), we get PrΨ_𝑛⁽¹⁾=Pr𝑎_𝑛−1,𝑎⁽⁰⁾_𝑛−1=Pr𝑎⁽⁰⁾_𝑛−1∣𝑎_𝑛−1Pr𝑎_𝑛−1=12Pr𝑎⁽⁰⁾_𝑛−1∣𝑎_𝑛−1. (26) Since Pr𝑎⁽⁰⁾_𝑛−1∣𝑎_𝑛−1=𝑃_𝑒⁽⁰⁾,𝑎⁽⁰⁾_𝑛−1≠𝑎_𝑛−1, (27) with 𝑃_𝑒⁽⁰⁾ being the symbol error probability of the first iteration, the probability (26) results 𝑃𝜓^(1,0)=𝑃𝜓^(1,3)=121−𝑃_𝑒⁽⁰⁾,𝑃𝜓^(1,1)=𝑃𝜓^(1,2)=12𝑃_𝑒⁽⁰⁾. (28) Generalizing, for 𝑖>0 it is possible to show that 𝑃𝜓^(𝑖,0)=𝑃𝜓^(𝑖,3)=121−𝑃_𝑒^(𝑖−1),𝑃𝜓^(𝑖,1)=𝑃𝜓^(𝑖,2)=12𝑃_𝑒^(𝑖−1). (29)

On the other hand, taking into account that 𝑔𝑎_𝑛,𝜓^(𝑖,0)=𝑔𝑎_𝑛,𝜓^(𝑖,3)=𝑎_𝑛,𝑔𝑎_𝑛,𝜓^(𝑖,1)=𝑎_𝑛𝑔𝑎+2,_𝑛,𝜓^(𝑖,2)=𝑎_𝑛−2, (30) it is possible to verify that 𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,0)=𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,3)=1√𝑒2𝜋𝜎^{−(1/2𝜎2)(𝑦𝑛(𝑖)−𝑎𝑛)2},𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,1)=1√𝑒2𝜋𝜎^{−(1/2𝜎2)(𝑦𝑛(𝑖)−𝑎𝑛−2)2},𝑓_{𝑦∣𝑎,Ψ}𝑦_𝑛^(𝑖)∣𝑎_𝑛,𝜓^(𝑖,2)=1√𝑒2𝜋𝜎^{−(1/2𝜎2)(𝑦𝑛(𝑖)−𝑎𝑛+2)2}. (31)(32)(33) Thus, at high SNR (i.e., 1/𝜎≫1), from (19)–(33) it is possible to show that 𝑃_𝑒^(𝑖)=12Pr𝑦_𝑛^(𝑖)<0∣𝑎_𝑛=+1+Pr𝑦_𝑛^(𝑖)≥0∣𝑎_𝑛1=−1=𝑄𝜎+12𝑃_𝑒^(𝑖−1)11−𝑄𝜎+12𝑃_𝑒^(𝑖−1)𝑄3𝜎1≈𝑄𝜎+12𝑃_𝑒^(𝑖−1), (34) where 𝑄(𝑥)=1√2𝜋^∞𝑥𝑒^−𝑡2/2𝑑𝑡. (35)

Operating on the recursive form of the error probability (34), it is simple to verify that 𝑃_𝑒^(𝑖)1≈2𝑄𝜎,𝑖≫1. (36) Since the error probability of the DFE with error propagation is given by [3] 𝑃^DFE_𝑒≃2^𝐿𝑄1𝜎, (37) from (36) we can conclude that for a number of iterations sufficiently large, the performance of the DFFE in the presence of a duobinary channel (i.e., 𝐿=1) is reduced to that achieved by the DFE with error propagation. As we shall show later, the proper number of iterations depends strongly on both the noise power and the channel dispersion. Finally, we realize that the conclusions derived from this example can be extended for channels with memory 𝐿>1.

3.2. Simulation Results

A theoretically based estimation of the error probability provides an effective tool for designing the DFFE parameters. The design process is simple and consists of two main steps.(i)Estimate the number of taps for the feedforward and feedback filters according to the expected channel response (similarly to the design of the DFE).(ii)Estimate the number of the DFFE iterations based on performance evaluation. This task can be also achieved by using computer simulations. As initial point, set 𝑅=𝐿+1.

Figure 3 shows the contour of the BER as a function of the SNR and the iteration number. In this case, we use a postcursor ISI channel defined by 𝑑_𝑘=𝛼^𝑘, 0<𝑘≤𝐿 with 𝛼=0.5, 𝐿=6, and 𝑅=20. We can observe that the performance of the DFFE for 𝑅>6 is similar in all iterations. Therefore, we conclude that DFFE with 𝑅=𝐿+1 achieves the same performance as the traditional DFE, as it can be verified from Figure 4. For the DFFE, note the excellent agreement between the values derived from computer simulations and the theoretical prediction given by (16).

Figure 3 

BER versus SNR and number of iterations. Postcursor channel with 𝛼=0.5/𝐿=6.

Figure 4 

Performance of DFFE with 𝑅=7 and DFE. Postcursor channel with 𝛼=0.5/𝐿=6.

The performance of the DFE and an adaptive DFFE with 𝑅=𝐿+1 iterations in the presence of different dispersive channels is evaluated in Figure 5. We consider four channels: 𝛼=0.6,0.82,0.92, and 0.95 with 𝐿=10, 30, 60, and 100, respectively. The adaptive DFFE has been implemented with the least mean square (LMS) algorithm [3] by using the final decision to estimate the error signal. In all cases, it can be observed that DFFE and DFE achieve essentially the same performance. This result agrees with the theoretical analysis presented in the Appendix, where the impact of imperfect channel estimation on the performance of DFE and DFFE is investigated.

Figure 5 

Performance of DFE and adaptive DFFE with 𝑅=𝐿+1 for different postcursor ISI channels.

4. Parallel Implementation and Complexity

4.1. Parallel-Processing DFFE Architecture

As mentioned in Section 1, the DFFE breaks the bottleneck created by the feedback loop of the DFE using tentative decisions in a feedforward fashion. This enables pipelined implementations which are able to operate at high clock rates. Moreover, parallel processing can be used to further increase the throughput and achievable data rate of the DFFE-based receiver. A 𝑃-way parallel implementation is shown in Figure 6. Using this architecture, the data rate and throughput may be increased by a factor 𝑃 with growth in complexity linear in 𝑃.

Figure 6 

Parallel DFFE architecture for 𝑃=4 and 𝐿=3. Blocks DFFEn are as shown in Figure 1.

4.2. Complexity of DFFE

Table 1 shows the numbers of adders, registers, and multiplexers for the DFFE, computed under the following assumptions. The multipliers shown in Figure 1 were considered to be 2-to-1 multiplexers (it is assumed that both the positive and negative values of the coefficients 𝑑_𝑘 are available), which is a correct assumption for binary decisions with values ±1 (e.g., 2-pulse amplitude modulation (PAM) [3]). The number of adders for the DFFE was estimated assuming that the basic building block is a two-input adder.

Table 1 

Complexity of the parallel DFFE architecture for 2-PAM and 𝑅>𝐿.

Table 2 presents a comparison of the complexity of the DFFE with the DFE architectures proposed in [4, 7, 9, 10]. The numbers of adders and 2-to-1 multiplexers for the parallel DFE schemes were extracted from [4, 7, 9], while the number of registers was estimated based on their architectures. Figure 7 shows the numbers of the three types of components as functions of the number of feedback taps. The most important difference between the DFFE and the DFE proposals considered is that the former does not use look-ahead techniques or multiplexer loops, and this reduces the implementation complexity. In all the cases, the benefits of the DFFE are evident in the presence of highly dispersive channels (i.e., 𝐿≫1). A comparison of the complexity for 𝑀-PAM is shown in Table 3. We observe that the DFFE still provides a significant reduction of complexity with respect to the DFE architectures [7, 9]. (In 𝑀-PAM, multiplication operations are achieved by using 𝑀−1 2-to-1 muxes.) This conclusion can be extended to 𝑀-QAM where the complexity of both DFE and DFFE is approximately two times the one obtained with 𝑀-PAM.

Table 2 

Complexity comparison between parallel DFFE and DFE architectures for 2-PAM with 𝑅=𝐿+1 for 𝐿≫1.

Table 3 

Complexity comparison between parallel DFFE and DFE architectures for 𝑀-PAM with 𝑅=𝐿+1 for 𝐿≫1.

(a)

(b)

(c)

Figure 7 

Number of adders, registers, and 2-to-1 multiplexers versus the number of feedback taps 𝐿, for the parallel DFFE with 𝑅=𝐿+1 and DFE architectures proposed in [4, 7, 9, 10]. Parallelization factor: 𝑃=16. Modulation format: 2-PAM.

4.3. VLSI Implementation

We consider an application-specific integrated circuit (ASIC) implementation of the proposed DFFE in a 10Gb/s  2-PAM receiver. The DFFE architecture was succesfully synthetized (i.e., no timing issues) by using 28 nm CMOS technology with standard voltage threshold (SVT) transistors for 𝐿=5/10/30, 𝑃=16 (𝑓_clock=625.0MHz), and 𝑃=32 (𝑓_clock=312.5MHz) with 𝑅=𝐿+1 iterations. Multiplication operations were implemented by using 2-to-1 multiplexers. The number of bits of the input samples (𝑁_𝑖) and taps (𝑁_𝑐) has been derived from computer simulations for the different postcursor channels (i.e., 𝐿=5/10/30). We used 𝑁_𝑐=7 and 𝑁_𝑖=7 for 𝐿=5 and 10. For 𝐿=30, the number of bits of the input samples was increased to 𝑁_𝑖=8 (see Figure 8). Adders were implemented with carry propagation, thus 𝑁_𝑐+log₂(𝐿) bits are required to represent the sample at the slicer input. Finally, the slicer uses the MSB of the input sample to control the muxes in order to select the positive or negative coefficient.

Figure 8 

BER versus SNR for the DFFE with 𝐿=30, 𝑅=31, 𝑁𝑖=7/8 bits, and 𝑁𝑐=7 bits.

Table 4 shows the total number of cells and components normalized to the values of 𝑃=16 and 𝐿=5. Note that these results agree very well with the expected values derived from the complexity analysis developed in Section 4.2; that is, the complexity increases linearly with the parallelization factor (𝑃) and quadratically with the memory of channel 𝐿.

Table 4 

Synthesis results for parallel DFFE architecture for 2-PAM and 𝑅=𝐿+1 with 28 nm CMOS technology.

4.4. Analysis of the Critical Path

The speed of the different DFE architectures are related to their critical paths. The existing parallel DFE architectures of [4, 9, 10] are faster than the DFFE. However, they are not considered for a speed comparison as a result of their prohibitive high implementation complexity in the presence of channels with high ISI (𝐿≫1). On the other hand, the critical path of the less complex DFE solution proposed in [7] is given by 𝑇_DFE−[7]≈(1/(𝐿/2+1))𝑇_add+log₂(𝑀)𝑇_mux for 𝑀-PAM, where 𝑇_mux and 𝑇_add are the multiplexer and adder delays, respectively. Note that 𝑇_DFE−[7] is independent of the channel memory 𝐿. For example, for 28 nm CMOS technology, 𝑇_mux≈0.05ns and 𝑇_add≈0.10ns; therefore, the maximum data rates with 𝑃=1 for 2-PAM and 4-PAM are ~17.8 and 18.8 Gb/s, respectively.

The critical path for the DFFE is shown in Figure 1. Notice that the delay of the critical path given by 𝑇_DFFE≈𝐿𝑇_add+log₂(𝑀)𝑇_mux increases linearly with the memory channel. As it is shown in Section 4.3, no timing issues have been observed with 𝐿=30 and 𝑃=32 for 2-PAM with 𝑓_clock=312.5MHz by using 28 nm CMOS technology. Thus, the maximum data rates achieved by the DFFE for 2-PAM and 4-PAM are 10 and ~20 Gb/s (since 𝐿≫1 and 𝑇_mux<𝑇_add, note that 𝑇_DFFE is dominated by the term 𝐿𝑇_add. Therefore the impact of the increase of the constellation size (2→4) on the critical path will be small), respectively. On the other hand, for 𝐿=30 the relative complexity of the DFE [7] with 𝑃=1 (∝2𝑀^𝐿/2) with respect to the DFFE with 𝑃=32 (∝32(𝑀−1)𝐿²) is (a) 2×2^(30/2)/(32×30²)=2.28 for 2-PAM and (b) 2×4^(30/2)/(32×3×30²)=2.49×10⁴ for 4-PAM. Therefore, the DFFE is able to provide high data rates (e.g., >10 Gb/s) by using existing CMOS technology with complexity implementation lower than that derived from the less complex parallel DFE proposed in [7].

5. Conclusions

In this paper we have proposed and analyzed the DFFE, a low-complexity iterative equalization architecture for high-speed receivers which uses tentative decisions in a feedforward way to estimate postcursor ISI. This central feature lends itself well to a simple parallel implementation, resulting in a reduction of complexity. Using typical examples, we show that DFFE allows to obtain a similar performance to DFE architecture. Moreover, we have proposed a theoretical approximation to estimate the error probability which allows us to demonstrate that the DFFE reaches the same performance as DFE when the number of iterations increases. These advantages make the DFFE an excellent choice for high-speed receivers required to operate over highly dispersive channels. Furthermore, owing to the DFFE flexibility, the architecture can be combined with traditional linear feedforward equalizers or Viterbi algorithm (VA) [3] to compensate channel impairments in the presence of both pre- and postcursor ISI.

Appendix

Impact of Imperfect Channel Estimation

Since the DFFE is an attractive solution in the presence of channels with high ISI (i.e., 𝐿≫1), it is possible to show that the impact of an imperfect channel estimation is similar in both equalizers, that is, DFE and DFFE. The received input sample 𝑦_𝑛 can be expressed as 𝑦_𝑛=𝑎_𝑛+^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+𝑧_𝑛, (A.1) where 𝑑_𝑘 with 𝑘=1,…,𝐿 is the postcursor ISI tap, 𝑎_𝑛 is the transmitted symbol, and 𝑧_𝑛 is white Gaussian noise with power 𝜎². The signal (A.1) can be rewritten as 𝑦_𝑛=𝑎_𝑛+^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+𝑧_𝑛=𝑎_𝑛+^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+^𝐿_𝑘=1𝑎_𝑛−𝑘Δ_𝑘+𝑧_𝑛, (A.2) where 𝑑_𝑘 and Δ_𝑘 denote the tap estimated at the receiver and the error estimation, respectively (i.e., 𝑑_𝑘=𝑑_𝑘+Δ_𝑘). Since 𝐿≫1 and symbols 𝑎_𝑛 are assumed independent and identically distributed (iid), from the central limit theorem note that the term 𝑟_𝑛=^𝐿_𝑘=1𝑎_𝑛−𝑘Δ_𝑘 (A.3) can be modeled as a zero mean Gaussian random variable with variance 𝜎²_𝑟. Therefore, the signal at the input of the receiver with imperfect channel estimation can be seen as 𝑦_𝑛=𝑎_𝑛+^𝐿_𝑘=1𝑎_𝑛−𝑘𝑑_𝑘+𝑧_𝑛, (A.4) where 𝑧_𝑛=𝑟_𝑛+𝑧_𝑛 (A.5) is zero mean Gaussian noise with power 𝜎²_𝑟+𝜎². Thus, from (A.4) and (A.5) we can conclude that the impact of the imperfect channel estimation on the performance of DFE and DFFE will be similar.

Acknowledgments

This paper has been supported in part by the ANPCyT (PICT2008-1256, PRH-203), Fundación Tarpuy, and Fundación Fulgor.