A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Table 2

Complexity comparison between parallel DFFE and DFE architectures for 2-PAM with 𝑅=𝐿+1 for 𝐿≫1.

Component			Receiver
	DFFE (this work)	DFE [4]	DFE [7]	DFE [9]	DFE [10]
Adders	𝐿^2𝑃/2	2^𝐿𝑃	2^𝐿/22𝑃	2^𝐿𝑃	2^𝐿+1𝑃
Registers	𝐿^3𝑃/6	∼2^𝐿𝑃	∼2^𝐿/2(𝑃+1)	𝐿^2+2^𝐿𝑃	(2^𝐿+𝐿)𝑃
2-to-1 multiplexers	𝐿^2𝑃/2	(2^𝐿−1)𝑃	(2^𝐿/2−1)2𝑃	2^𝐿𝐿(𝑃−𝐿/2+𝑃/𝐿−1)	2^𝐿𝑃