A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Table 3

Complexity comparison between parallel DFFE and DFE architectures for 𝑀-PAM with 𝑅=𝐿+1 for 𝐿≫1.

Component		Receiver
	DFFE (this work)	DFE [7]	DFE [9]
Adders	𝐿^2𝑃/2	𝑀^𝐿/22𝑃	𝑀^𝐿𝑃
Registers	𝐿^3𝑃/6	∼𝑀^𝐿/2(𝑃+1)	𝐿^2+𝑀^𝐿𝑃
2-to-1 multiplexers	(𝑀−1)𝐿^2𝑃/2	(𝑀^𝐿/2−1)2𝑃	𝑀^𝐿𝐿(𝑃−𝐿/2+𝑃/𝐿−1)