Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA

Table 4

Resource utilization, speed of operations, and power consumption of the DCT design on synchronous FPGA and asynchronous FPGA implementations for various input fixed-point bus widths.

Fixed-point width	Xilinx Virtex-5 xc5vlx330 (synchronous)							Achronix SPD60 (asynchronous)				% Increase; in speed
	Slices	Slice FFs	Slice LUTs	Freq. (MHz)	Quies. power (W)	Dyn. power (W)	Total power (W)	RLBs	SEQ-DFFs	LUT4s	Freq. (MHz)
3	3262 (6%)	5310	9684	113.49	2.952	1.358	4.310	4531 (77.06%)	31352	36248	349.6	208.04
4	3684 (7%)	5811	10317	110.63	2.952	1.409	4.361	4852 (82.52%)	33767	38818	335.8	203.53
5	3786 (7%)	6082	10987	109.12	2.952	1.392	4.344	5174 (88%)	36193	41393	330.6	230.6
6	4032 (7%)	6516	11592	111.74	2.952	1.420	4.372	5496 (93.47%)	38609	43968	334.2	199.09
7	4080 (7%)	6925	12312	111.84	2.952	1.447	4.399	5772 (98.18%)	40974	46184	302.7	170.65
8	4341 (8%)	7407	12943	107.48	2.952	1.492	4.444	—	—	—	—	—