Research Article
Applying Partial Power-Gating to Direction-Sliced Network-on-Chip
Table 2
GEMS simulator configuration.
| Topology | 8 × 8 mesh, 1 core, and 1 L2Cache bank per node |
| Private L1Cache | 32 KB instruction & data cache, 4-way, 64 B/line, and LRU |
| Shared L2Cache | NUCA, 8-way, 64 banks, 512 KB/bank, 64 B/line, and LRU |
| Cache coherence | MOESI_CMP_Directory protocol |
| Memory controller | 8, connected with nodes 2, 5, 16, 23, 40, 47, 58, and 61 |
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