﻿<?xml version="1.0" encoding="utf-8"?><rss version="2.0"><channel><title>Journal of Electrical and Computer Engineering</title><link>http://www.hindawi.com</link><description>The latest articles from Hindawi Publishing Corporation</description><copyright>&amp;#169; 2012, Hindawi Publishing Corporation. All rights reserved.</copyright><item><title>Spectral Distortion in Lossy Compression of Hyperspectral Data</title><link>http://www.hindawi.com/journals/jece/2012/850637/</link><description>Distortion allocation varying with wavelength in lossy compression of hyperspectral imagery is investigated, with the aim of minimizing the spectral distortion between original and decompressed data. The absolute angular error, or spectral angle mapper (SAM), is used to quantify spectral distortion, while radiometric distortions are measured by maximum absolute deviation (MAD) for near-lossless methods, for example, differential pulse code modulation (DPCM), or mean-squared error (MSE) for lossy methods, for example, spectral decorrelation followed by JPEG 2000. Two strategies of interband distortion allocation are compared: given a target average bit rate, distortion may be set to be constant with wavelength. Otherwise, it may be allocated proportionally to the noise level of each band, according to the virtually lossless protocol. Comparisons with the uncompressed originals show that the average SAM of radiance spectra is minimized by constant distortion allocation to radiance data. However, variable distortion allocation according to the virtually lossless protocol yields significantly lower SAM in case of reflectance spectra obtained from compressed radiance data, if compared with the constant distortion allocation at the same compression ratio.</description><Author>Bruno Aiazzi, Luciano Alparone, Stefano Baronti, Cinzia Lastri, and Massimo Selva</Author><copyright>Copyright &amp;#xa9; 2012 Bruno Aiazzi et al. All rights reserved.</copyright></item><item><title>Developing a Fuzzy Logic Based on Demand Multicast Routing Protocol</title><link>http://www.hindawi.com/journals/jece/2012/389812/</link><description>Multicast routing is an efficient method to lead data packets from one source group to several nodes as destination group. Although multicast routing algorithms could be efficient in many situations but their routing mechanism like as route request flooding packets likely results in poor performance in comparison to unicast routing algorithms. In this research, two efficient methods are proposed to improve the performance of On Demand Multicast Routing Protocol (ODMRP). The main proposed method tries to establish a small, efficient, and high-quality forwarding group. This is achieved by augmenting the Join Query packets with additional information such as speed, power level of node, and link bandwidths. Besides, the control overhead is further reduced by restricting the domain of control packet flooding (by restricting the domain of control packet flooding). The performance evaluation shows that the proposed scheme increases the packet delivery rate by up to 40&amp;#37;, while reducing average end-to-end delay and consumed power by about 35&amp;#37; and 45&amp;#37;, respectively.</description><Author>Alireza Shams Shafigh, Kamran Abdollahi, and Marjan Kouchaki</Author><copyright>Copyright &amp;#xa9; 2012 Alireza Shams Shafigh et al. All rights reserved.</copyright></item><item><title>An Optimization Mechanism Intended for Static Power Reduction Using Dual-VthTechnique</title><link>http://www.hindawi.com/journals/jece/2012/561580/</link><description>Power consumption reduction is a challenge nowadays. Techniques for dynamic and static power minimization have been proposed, but most of them are very time consuming. This work proposes an algorithm for reducing static power, which can be perfectly inserted in the conventional design flow for integrated systems considering an open source environment (open access infrastructure). The proposed approach, based on a Dual-Threshold technique, replaces part of the cells of the circuit by cells with a higher threshold voltage without resulting in timing violations in the circuit. The decision to replace a cell is based on timing estimates of the circuit modeling with the cell replacement, before it is actually replaced. The fact that only some cells are replaced every iteration results in a reduction of the runtime of the algorithm. Additionally, results showed a reduction in static power up to 39.28&amp;#37;, when applying the proposed approach in the ISCAS85 benchmark circuits.</description><Author>Rodolfo P. Santos, Gabriela S. Clemente, Abel Silva-Filho, Cristiano Ara&amp;#250;jo, Adriano Sarmento, Manoel Lima, and Edna Barros</Author><copyright>Copyright &amp;#xa9; 2012 Rodolfo P. Santos et al. All rights reserved.</copyright></item><item><title>Characterization of Hardware Impairments in Multiple Antenna Systems for DoA Estimation</title><link>http://www.hindawi.com/journals/jece/2011/908234/</link><description>We consider the effects introduced by hardware impairments on the estimation of the direction of arrival (DoA) deploying a multiple antenna radio system. We derive a system model from experimental measurements of a state-of-the-art hardware test bed based on an RF direct-conversion architecture. The system model includes DC offsets, carrier frequency and phase offsets, and the phase noise. Then, we propose a simple digital compensation algorithm of the impairments for bidimensional DoA estimation (azimuth and elevation) with a 3D orthogonal linear array. The robustness of the algorithm in terms of minimum-mean-squared error as a function of the hardware impairments is evaluated and compared with that achieved using the root-MUSIC algorithm.</description><Author>Daniele Inserra and Andrea M. Tonello</Author><copyright>Copyright &amp;#xa9; 2011 Daniele Inserra and Andrea M. Tonello. All rights reserved.</copyright></item><item><title>Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing</title><link>http://www.hindawi.com/journals/jece/2011/361384/</link><description>A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201&amp;#x2009;MHz. The proposed block is implemented using 0.25&amp;#x2009;&amp;#x3bc;m TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.</description><Author>Neeta Pandey and Sajal K. Paul</Author><copyright>Copyright &amp;#xa9; 2011 Neeta Pandey and Sajal K. Paul. All rights reserved.</copyright></item><item><title>Single CDTA-Based Current Mode All-Pass Filter and Its Applications</title><link>http://www.hindawi.com/journals/jece/2011/897631/</link><description>This paper presents a single current difference transconductance amplifier (CDTA) based all-pass current mode filter. The proposed configuration makes use of a grounded capacitor which makes it suitable for IC implementation. Its input impedance is low and output impedance is high, hence suitable for cascading. The circuit does not use any matching constraint. The nonideality analysis of the circuit is also given. Two applications, namely, a quadrature oscillator and a high Q band pass filter are developed with the proposed circuit. The functionality of the circuit is verified with SPICE simulation using 0.35&amp;#x2009;&amp;#x03BC;m TSMC CMOS technology parameters.</description><Author>Neeta Pandey and Sajal K. Paul</Author><copyright>Copyright &amp;#xa9; 2011 Neeta Pandey and Sajal K. Paul. All rights reserved.</copyright></item><item><title>A Review of Wireless and PLC Propagation Channel Characteristics for Smart Grid Environments</title><link>http://www.hindawi.com/journals/jece/2011/154040/</link><description>Wireless, power line communication (PLC), fiber optic, Ethernet, and so forth are among the communication technologies on which smart grid communication infrastructure is envisioned to be built. Among these, wireless and PLC-based solutions are attractive considering the cost of initial deployment. Wireless communication deployment in smart grid covers a variety of environments such as indoor, outdoor, and electric-power-system facilities. Similar diversity is expected in PLC deployment as well covering low voltage (LV), medium voltage (MV), and high voltage (HV) segments of the grid. In spite of being attractive, wireless and PLC channels are very harsh posing great challenges to performance of communication systems. In proposing solutions to smart grid communication needs, two approaches are likely to be followed. One is based on the use of existing wireless and PLC technologies with some modifications, and the other relies upon developing novel communication protocols particularly addressing the smart grid needs. Both of these approaches require an in-depth knowledge of communication channel characteristics. The aim of this study is to reveal the wireless and PLC channel characteristics of smart grid environments in terms of several parameters such as path loss and attenuation, time dispersion, time selectivity, amplitude statistics, and noise characteristics.</description><Author>Sabih G&amp;#252;zelg&amp;#246;z, H&amp;#252;seyin Arslan, Arif Islam, and Alexander Domijan</Author><copyright>Copyright &amp;#xa9; 2011 Sabih G&amp;#xfc;zelg&amp;#xf6;z et al. All rights reserved.</copyright></item><item><title>A New Efficient Ordering Scheme for Sphere Detection</title><link>http://www.hindawi.com/journals/jece/2011/821407/</link><description>The decoding order has a deep impact in the complexity of sphere detection. A new ordering scheme for sphere detection is presented in this paper, which is based on SIC (serial interference canceling) and the gradient defined by the accumulated probability of the absolute difference between symbol element and the zero-forcing solution. The simulation results show that the proposed ordering scheme can achieve a significant complexity reduction, especially for high numbers of antennas and large constellation sizes in the low SNR region. Compared with sphere detection complexity under BSQR (balanced sorted QR) decomposition and GB (gradient-based) orderings at SNR=5&amp;#x2009;dB, the average number of visited nodes under our proposed ordering is reduced by almost 30&amp;#37; and 33&amp;#37; in 4&amp;#x00D7;4 16QAM system and by almost 30&amp;#37; and 50&amp;#37; reduction in 6&amp;#x00D7;6 16QAM system, respectively. For 4&amp;#x00D7;4 64QAM system, almost 75&amp;#37; and 80&amp;#37; reduction at SNR=0&amp;#x2009;dB and more than 40&amp;#37; and 50&amp;#37; reduction at SNR=5&amp;#x2009;dB can be achieved, respectively.</description><Author>Cao Haiyan and Li Jun</Author><copyright>Copyright &amp;#xa9; 2011 Cao Haiyan and Li Jun. All rights reserved.</copyright></item><item><title>Camera Localization in Distributed Networks Using Trajectory Estimation</title><link>http://www.hindawi.com/journals/jece/2011/604647/</link><description>This paper presents an algorithm for camera localization
using trajectory estimation (CLUTE) in a distributed
network of nonoverlapping cameras. The algorithm recovers the
extrinsic calibration parameters, namely, the relative position and
orientation of the camera network on a common ground plane
coordinate system. We first model the observed trajectories in
each camera&amp;#39;s field of view using Kalman filtering, then we use
this information to estimate the missing trajectory information
in the unobserved areas by fusing the results of a forward and
backward linear regression estimation from adjacent cameras.
These estimated trajectories are then filtered and used to recover
the relative position and orientation of the cameras by analyzing
the estimated and observed exit and entry points of an object in
each camera&amp;#39;s field of view. The final configuration of the network
is established by considering one camera as a reference and by
adjusting the remaining cameras with respect to this reference.
We demonstrate the algorithm on both simulated and real data
and compare the results with state-of-the-art approaches. The
experimental results show that the proposed algorithm is more
robust to noisy and missing data and in case of camera failure.</description><Author>Nadeem Anjum</Author><copyright>Copyright &amp;#xa9; 2011 Nadeem Anjum. All rights reserved.</copyright></item><item><title>A Cache Architecture for Counting Bloom Filters: Theory and Application</title><link>http://www.hindawi.com/journals/jece/2011/475865/</link><description>Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, for example, utilizing multilevel memory hierarchies, special hardware architectures, and hardware threading. In this paper, we introduce a multilevel memory architecture for counting Bloom filters. Based on the probabilities of incrementing of the counters in the counting Bloom filter, a multi-level cache architecture called the cached counting Bloom filter (CCBF) is presented, where each cache level stores the items with the same counters. To test the CCBF architecture, we implement a software packet classifier that utilizes basic tuple space search using a 3-level CCBF. The results of mathematical analysis and implementation of the CCBF for packet classification show that the proposed cache architecture decreases the number of memory accesses when compared to a standard Bloom filter. Based on the mathematical analysis of CCBF, the number of accesses is decreased by at least 53&amp;#x25;. The implementation results of the software packet classifier are at most 7.8&amp;#x25; (3.5&amp;#x25; in average) less than corresponding mathematical analysis results. This difference is due to some parameters in the packet classification application such as number of tuples, distribution of rules through the tuples, and utilized hashing functions.</description><Author>Mahmood Ahmadi and Stephan Wong</Author><copyright>Copyright &amp;#xa9; 2011 Mahmood Ahmadi and Stephan Wong. All rights reserved.</copyright></item><item><title>Unsupervised 3D Prostate Segmentation Based on Diffusion-Weighted Imaging MRI Using Active Contour Models with a Shape Prior</title><link>http://www.hindawi.com/journals/jece/2011/410912/</link><description>Accurate estimation of the prostate location and volume from in vivo images
plays a crucial role in various clinical applications. Recently, magnetic resonance imaging (MRI) is proposed as a promising modality to detect and monitor prostate-related diseases. In this paper, we propose an unsupervised algorithm to segment prostate with 3D apparent diffusion coefficient (ADC) images derived from diffusion-weighted imaging (DWI) MRI without the need of a training dataset, whereas previous methods for this purpose require training datasets. We first apply a coarse segmentation to extract the shape information. Then, the shape prior is incorporated into the active contour model. Finally, morphological operations are applied to refine the segmentation results. We apply our method to an MR dataset obtained from three patients and provide segmentation results obtained by our method and an expert. Our experimental results show that the performance of the proposed method is quite successful.</description><Author>Xin Liu, Masoom A. Haider, and Imam Samil Yetik</Author><copyright>Copyright &amp;#xa9; 2011 Xin Liu et al. All rights reserved.</copyright></item><item><title>New  Low-Power Tristate  Circuits in Positive Feedback  Source-Coupled  Logic</title><link>http://www.hindawi.com/journals/jece/2011/670508/</link><description>Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both  techniques have been developed and simulated using 0.18&amp;#x2009;&amp;#x3bc;m CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.</description><Author>Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, and Maneesha Gupta</Author><copyright>Copyright &amp;#xa9; 2011 Kirti Gupta et al. All rights reserved.</copyright></item><item><title>MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications</title><link>http://www.hindawi.com/journals/jece/2011/150354/</link><description>This paper introduces a floating inductance simulation using multiple output current controlled current conveyer transconductance amplifier (MO-CCCCTA). The simulated inductor retains minimum requirement of passive elements as only one-grounded capacitance is used for one inductor. PSPICE simulation has been done and included to ensure the validity of the approach. A few applications have also been included to substantiate the usability of the proposed circuit.</description><Author>Neeta Pandey, Rishik Bazaz, and Rahul Manocha</Author><copyright>Copyright &amp;#xa9; 2011 Neeta Pandey et al. All rights reserved.</copyright></item><item><title>Circuit Distortion Analysis Based on the Simplified Newton&amp;#39;s Method</title><link>http://www.hindawi.com/journals/jece/2011/540305/</link><description>A new computational technique for distortion analysis of nonlinear circuits is presented. The new technique is applicable to the same class of circuits, namely, weakly nonlinear and time-varying circuits, as the periodic Volterra series. However, unlike the Volterra series, it does not require the computation of the second and third derivatives of device models. The new method is computationally efficient compared with a complete multitone nonlinear steady-state analysis such as harmonic balance. Moreover, the new technique naturally allows computing and characterizing the contributions of individual circuit components to the overall circuit distortion. This paper presents the theory of the new technique, a discussion of the numerical aspects, and numerical results.</description><Author>M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, and B. J. Mulvaney</Author><copyright>Copyright &amp;#xa9; 2011 M. M. Gourary et al. All rights reserved.</copyright></item><item><title>The Effect of Intermittent Signal on the Performance of Code Tracking Loop in GNSS Receivers</title><link>http://www.hindawi.com/journals/jece/2011/418032/</link><description>This paper analyzes the code tracking performance in the presence of signal blanking in Global Navigation Satellite System (GNSS). The blanking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal blanking is used to remove random or periodic interference. Nevertheless, the effect of temporary discontinuity of signal often leads to the tracking and position error. To analyze this problem, three types of blanking model are considered: no blanking, periodic blanking, and random blanking of the signals input into the code tracking loop. The mean time to lose lock (MTLL) is to assess the performance of code tracking system under signal blanking. Finally, the effect of steady-state tracking errors on the performance of tracking loop resulting from blanking environment is also discussed.</description><Author>Chung-Liang Chang</Author><copyright>Copyright &amp;#xa9; 2011 Chung-Liang Chang. All rights reserved.</copyright></item><item><title>New Topologies of Lossless Grounded Inductor Using OTRA</title><link>http://www.hindawi.com/journals/jece/2011/175130/</link><description>Two alternate topologies of lossless grounded inductor have been proposed using operational transresistance amplifier (OTRA). Three applications using the proposed inductors are also included.  PSPice simulation and experimental results have been included to demonstrate the performance and verify the theoretical analysis.</description><Author>Rajeshwari Pandey, Neeta Pandey, Sajal K. Paul, A. Singh, B. Sriram, and K. Trivedi</Author><copyright>Copyright &amp;#xa9; 2011 Rajeshwari Pandey et al. All rights reserved.</copyright></item><item><title>Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators</title><link>http://www.hindawi.com/journals/jece/2011/586853/</link><description>Multiphase sinusoidal oscillator circuits are presented which utilize Operational Transresistance Amplifier (OTRA) as the active element. The first circuit produces n odd-phase oscillations of equal amplitudes and equally spaced in phase. The second circuit is capable of producing n odd- or even- phase oscillations equally spaced in phase. An alternative approach is discussed in the third circuit, which utilizes a single-phase tunable oscillator circuit which is used to inject signals into a phase shifter circuits. An automatic gain control (AGC) circuit has been implemented for the second and third circuit. The circuits are simple to realize and have a low component count. PSPICE simulations have been given to verify the theoretical analysis. The experimental outcome corroborates the theoretical propositions and simulated results.</description><Author>Rajeshwari Pandey, Neeta Pandey, Mayank Bothra, and Sajal K. Paul</Author><copyright>Copyright &amp;#xa9; 2011 Rajeshwari Pandey et al. All rights reserved.</copyright></item><item><title>Desktop Software for Patch-Clamp Raw Binary Data Conversion and Preprocessing</title><link>http://www.hindawi.com/journals/jece/2011/251215/</link><description>Since raw data recorded by patch-clamp systems are always stored in binary format, electrophysiologists may experience difficulties with patch clamp data preprocessing especially when they want to analyze by custom-designed algorithms. In this study, we present desktop software, called PCDReader, which could be an effective and convenient solution for patch clamp data preprocessing for daily laboratory use. We designed a novel class module, called clsPulseData, to directly read the raw data along with the parameters recorded from HEKA instruments without any other program support. By a graphical user interface, raw binary data files can be converted into several kinds of ASCII text files for further analysis, with several preprocessing options. And the parameters can also be viewed, modified and exported into ASCII files by a user-friendly Explorer style window. The real-time data loading technique and optimized memory management programming makes PCDReader a fast and efficient tool. The compiled software along with the source code of the clsPulseData class module is freely available to academic and nonprofit users.</description><Author>Ning Zhang, Yutao Tian, Lei Zhang, Zhuo Yang, Tao Zhang, and Jishou Ruan</Author><copyright>Copyright &amp;#xa9; 2011 Ning Zhang et al. All rights reserved.</copyright></item><item><title>Effect of Correlated Non-Gaussian Quadratures on the Performance of Binary Modulations</title><link>http://www.hindawi.com/journals/jece/2011/176486/</link><description>The received signal in many wireless communication systems comprises of the sum of waves with random amplitudes and random phases. In general, the composite signal consists of correlated nonidentical Gaussian quadrature components due to the central limit theorem (CLT). However, in the presence of a small number of random waves, the CLT may not always hold and the quadrature components may not be Gaussian distributed. In this paper, we assume that the fading environment is such that the quadrature components follow a correlated bivariate Student-t joint distribution. Then, we derive the envelope distribution of the received signal and obtain new expressions for the exact and high signal-to-noise (SNR) approximate average BER for binary modulations. It also turns out that the derived envelope pdf approaches the Rayleigh and Hoyt distributions as limiting cases. Using the derived envelope pdf, we investigate the effect of correlated nonidentical quadratures on the error rate performance of digital communication systems.</description><Author>Valentine A. Aalo and George P. Efthymoglou</Author><copyright>Copyright &amp;#xa9; 2011 Valentine A. Aalo and George P. Efthymoglou. All rights reserved.</copyright></item><item><title>The Generalization of the Extra Element Theorem for Symbolic Circuit Tolerance Analysis</title><link>http://www.hindawi.com/journals/jece/2011/652706/</link><description>A new method of the symbolic circuit tolerance analysis has been proposed. The approach is based on Middlebrook&amp;#39;s extra element theorem and the generalized parameter extraction method. It does not need the matrix network description or presentation as algebraic sets or topological graphs. The proposed techniques have been realized in the computer program (Toleralize). To verify the theoretical analysis, computer simulation results are included.</description><Author>Vladimir Filaretov and Konstantin Gorshkov</Author><copyright>Copyright &amp;#xa9; 2011 Vladimir  Filaretov and Konstantin Gorshkov. All rights reserved.</copyright></item><item><title>Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison</title><link>http://www.hindawi.com/journals/jece/2011/189434/</link><description>Hierarchical interconnection networks (HINs) provide a framework for designing networks with reduced link cost by taking advantage of the locality of communication that exists in parallel applications. HINs employ multiple levels.  Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs provide fault tolerance in the presence of some faulty nodes and/or links. Existing HINs can be broadly classified into two classes. those that use nodes and/or links replication and those that use standby interface nodes. The first class includes Hierarchical Cubic Networks, Hierarchical Completely Connected Networks, and Triple-based Hierarchical Interconnection Networks. The second HINs class includes Modular Fault-Tolerant Hypercube Networks and Hierarchical Fault-Tolerant Interconnection Network. This paper presents a review and comparison of the topological properties of both classes of HINs. The topological properties considered are network degree, diameter, cost and packing density. The outcome of this study show among all HINs two networks that is, the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH), belonging to the first HIN class provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n,n) provide the best packing density, that is, the smallest chip area required for VLSI implementation.</description><Author>Mostafa Abd-El-Barr and Turki F. Al-Somani</Author><copyright>Copyright &amp;#xa9; 2011 Mostafa Abd-El-Barr and Turki F. Al-Somani. All rights reserved.</copyright></item><item><title>Optimal Hidden Node Area for Enhancing Routing Protocol Performance in IEEE 802.11 Multihop MANETs</title><link>http://www.hindawi.com/journals/jece/2011/402308/</link><description>The prevalence of hidden node areas in IEEE 802.11 multihop MANETs continues to hinder the performance of routing protocols. This letter presents an analytical model that relates the hidden node area to the hop distance between two communicating nodes. Unlike descriptions from the literature, we describe the hidden node area in terms of multiple layers and the different levels of interference contributed by each layer. We then develop mathematical expressions to determine the probability of successful delivery and end-to-end delay of a packet transmitted over multiple hops to a receiver node exposed to hidden nodes, as a function of hop distance. The numerical results show that decreasing the hop distance increases the probability of successful packet reception at a receiver, at the cost of increased end-to-end delay. However, using a specified delay objective, routing protocols can institute a hop distance threshold metric to limit the number of transmissions that produce collisions in the hidden node area and, thus, maximize their performance.</description><Author>Emeka Egbogah, Liqi Shi, and Abraham Fapojuwo</Author><copyright>Copyright &amp;#xa9; 2011 Emeka Egbogah et al. All rights reserved.</copyright></item><item><title>Analysis of the Consecutive Mean Excision Algorithms</title><link>http://www.hindawi.com/journals/jece/2010/459623/</link><description>The backward and forward consecutive mean excision (CME/FCME) algorithms are diagnostic methods for outlier (signal) detection. Since they are computationally simple, they have applications for both narrowband signal detection in cognitive radios and interference suppression. In this paper, a theoretical performance analysis framework of the CME algorithms is presented. The analysis provides simple tests of the detectability of the signals based on their shape in the considered domain (e.g., spectrum). As a consequence, results can be used to quickly check whether the CME/FCME algorithms are usable for a given problem or not without the need to resort to time consuming computer simulations. The computer simulations for random and orthogonal frequency division multiplexing (OFDM) signals show that the presented analysis is able to predict the detectability of signals well.</description><Author>Johanna Vartiainen, Janne Lehtom&amp;#228;ki, Harri Saarnisaari, and Markku Juntti</Author><copyright>Copyright &amp;#xa9; 2010 Johanna Vartiainen et al. All rights reserved.</copyright></item><item><title>A Modified Fast Approximated Power Iteration Subspace Tracking Method for Space-Time Adaptive Processing</title><link>http://www.hindawi.com/journals/jece/2010/973718/</link><description>We propose a subspace-tracking-based space-time adaptive processing technique for airborne radar applications. By applying a modified approximated power iteration subspace tracing algorithm, the principal subspace in which the clutter-plus-interference reside is estimated. Therefore, the moving targets are detected by projecting the data on the minor subspace which is orthogonal to the principal subspace. The proposed approach overcomes the shortcomings of the existing methods and has satisfactory performance. Simulation results confirm that the performance improvement is achieved at very small secondary sample support, a feature that is particularly attractive for applications in heterogeneous environments.</description><Author>Yang Zhiwei, He Shun, Liao Guisheng, and Ouyang Shan</Author><copyright>Copyright &amp;#xa9; 2010 Yang Zhiwei et al. All rights reserved.</copyright></item><item><title>Revisiting Sum of Residues Modular Multiplication</title><link>http://www.hindawi.com/journals/jece/2010/657076/</link><description>In the 1980s, when the introduction of public key
cryptography spurred interest in modular multiplication, many
implementations performed modular multiplication using a sum
of residues. As the field matured, sum of residues modular
multiplication lost favor to the extent that all recent surveys
have either overlooked it  or incorporated it within a larger class
of reduction algorithms.
In this paper, we present a new taxonomy of modular multiplication
algorithms. We include sum of residues as one of four
classes  and argue why it should be considered different to the
other, now more common, algorithms. We then apply techniques
developed for other algorithms to reinvigorate sum of residues
modular multiplication. We compare FPGA implementations of
modular multiplication up to 24 bits wide. The sum of residues
multipliers demonstrate reduced latency at nearly 50% compared
to Montgomery architectures at the cost of nearly doubled circuit
area. The new multipliers are useful for systems based on the
Residue Number System (RNS).</description><Author>Yinan Kong and Braden Phillips</Author><copyright>Copyright &amp;#x00A9; 2010 Yinan Kong and Braden Phillips. All rights reserved.</copyright></item><item><title>A Probabilistic Protocol for Multihop Routing in VANETs</title><link>http://www.hindawi.com/journals/jece/2010/185791/</link><description>Vehicular ad hoc networks (VANETs) allow communications over sequences of vehicles with radio devices. There are many possible applications over a VANET such as traffic jam warning, collision warning, parking lot reservations, camera
picture feed , and so forth. There have been quite a few results in the area seeking for a fast and reliable communication protocol due to
their potential. VANETs, however, are pointed out as difficult for numerical optimizations due to frequent changes in their
topologies. As a result, heuristic methods such as GPSR have been mainly used for routing packets over multihop communications.
In this paper, we present an algorithm to precompute the probability that  communication is possible between specified
source and destination in a VANET, under certain mathematical assumption. The proposed new protocol for multihop communication
refers to a lookup table containing the precomputed data to decide a good packet forwarder quickly.
We create a simulation testbed that seems challenging for all the existing multihop routing protocols for VANETs, in which we
test ours. We see much improved performances over GPSR after the algorithm is refined for some practical issues.</description><Author>Junichiro Fukuyama</Author><copyright>Copyright &amp;#xa9; 2010 Junichiro Fukuyama. All rights reserved.</copyright></item><item><title>Two New Families of Floating FDNR Circuits</title><link>http://www.hindawi.com/journals/jece/2010/563761/</link><description>Two new configurations for realizing ideal floating frequency-dependent negative resistor elements (FDNR) are introduced. The proposed circuits are symmetrical and are realizable by four CCII or ICCII or a combination of both. Each configuration is realizable by eight different circuits. Simulation results are included to support the theory.</description><Author>Ahmed M. Soliman and Ramy A. Saad</Author><copyright>Copyright &amp;#xa9; 2010 Ahmed M. Soliman and Ramy A. Saad. All rights reserved.</copyright></item><item><title>Acoustic Echo Cancellation Embedded in Smart Transcoding Algorithm between 3GPP AMR-NB Modes</title><link>http://www.hindawi.com/journals/jece/2010/902569/</link><description>Acoustic Echo Cancellation (AEC) is a necessary feature for mobile devices when the acoustic coupling between the microphone and the loudspeaker affects the communication quality and intelligibility. When implemented inside the network, decoding is required to access the corrupted signal. The AEC performance is strongly degraded by nonlinearity introduced by speech codecs. The Echo Return Loss Enhancement (ERLE) can be less than 10&amp;#x2009;dB for low bit rate speech codecs. We propose in this paper a coded domain AEC integrated in a smart transcoding strategy which directly modifies the Code Excited Linear Prediction (CELP) parameters. The proposed system addresses simultaneously problems due to network interoperability and network voice quality enhancement. The ERLE performance of this new approach during transcoding between Adaptive Multirate-NarrowBand (AMR-NB) modes is above 45&amp;#x2009;dB as required in Global System for Mobile Communications (GSM) specifications.</description><Author>Emmanuel Rossignol Thepie Fapi, Dominique Pastor, Christophe Beaugeant, and Herv&amp;#233; Taddei</Author><copyright>Copyright &amp;#xa9; 2010 Emmanuel Rossignol Thepie Fapi et al. All rights reserved.</copyright></item><item><title>Optimization Techniques for Verification of Out-of-Order Execution Machines</title><link>http://www.hindawi.com/journals/jece/2010/515021/</link><description>We develop two optimization techniques, flush-machine and collapsed flushing, to improve the efficiency of automatic refinement-abased verification of out-of-order (ooo) processor models. Refinement is a notion of equivalence that can be used to check that an ooo processor correctly implements all behaviors of its instruction set architecture (ISA), including deadlock detection. The optimization techniques work by reducing the computational complexity of the refinement map, a function central to refinement proofs that maps ooo processor model states to ISA states. This has a direct impact on the efficiency of verification, which is studied using 23 ooo processor models. Flush-machine, is a novel optimization technique. Collapsed flushing has been employed previously in the context of in-order processors. We show how to apply collapsed flushing for ooo processor models. Using both the optimizations together, we can handle 9 ooo models that could not be verified using standard flushing. Also, the optimizations provided a speed up of 23.29 over standard flushing.</description><Author>Sudarshan K. Srinivasan</Author><copyright>Copyright &amp;#xa9; 2010 Sudarshan K. Srinivasan. All rights reserved.</copyright></item><item><title>Channel Characterization for 700&amp;#x2009;MHz DSRC Vehicular Communication</title><link>http://www.hindawi.com/journals/jece/2010/840895/</link><description>Adapting OFDM for vehicular communication
requires extensive knowledge of anticipated multipath and
Doppler environments. We present a GPS-enabled channel
sounding system built and used to conduct a channel
measurement campaign. Tests conducted at the 700&amp;#x2009;MHz
band in and around downtown Ann Arbor, Michigan,
explored various vehicle-to-vehicle and vehicle-to-roadside
channel scenarios. The measured channel metrics are used
to quantify the effects on guard interval, packet duration,
and subcarrier spacing for a functional OFDM system
at 700&amp;#x2009;MHz. This paper is one of the first to present
vehicular-based channel-modeling results from measured
data in the 700&amp;#x2009;MHz band.</description><Author>Raffi Sevlian, Carl Chun, Ian Tan, Ahmad Bahai, and Ken Laberteaux</Author><copyright>Copyright &amp;#xa9; 2010 Raffi Sevlian et al. All rights reserved.</copyright></item></channel></rss>
