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CMOS Extension Technology: Materials, Devices, and Circuits

Call for Papers

Over the past few decades, complementary metal-oxide-semiconductor (CMOS) scaling by 30% in size every two years has been successfully achieved in semiconductor industry. Especially, every other CMOS technology node at sub-100-nm nodes, unprecedented technical innovation, has enabled us to complete the CMOS technology development in time (e.g., 1st generation stress engineering for 90 nm technology, high-k/metal-gate (HK/MG) gate stack for 45 nm technology, and advanced device structure like FinFET and Fully-Depleted Silicon-On-Insulator MOSFET for 22 nm technology). However, power supply voltage (VDD) has been stagnantly scaled down, so that power consumption in integrated circuits (ICs) has soared up, stemming from nonscalability of the thermal voltage (kBT/q) and/or the Boltzmann statistics. To overcome the fundamental barrier in CMOS scaling at 10-nm node and below, novel devices employing various turn-on mechanisms other than the thermionic emission mechanism have been proposed such as Tunnel FET (TFET), Feedback FET (FBFET), Nanoelectromechanical FET (NEMFET), and Negative capacitance FET.

We invite authors to submit original research as well as review articles that will stimulate the continuing efforts to develop, analyze, and model novel electron devices as CMOS Extension Technology. This special issue primarily focuses on CMOS Extension Technology. Potential topics include, but are not limited to:

  • Silicon-/Germanium-based semiconductor devices including FinFETs, ultra-thin-body SOI MOSFETs, gate-all-around MOSFETs, and nanowires
  • Steep-switching devices including Tunnel FET, Feedback FET, Nanoelectromechanical FET, and Negative Capacitance FET
  • Novel devices using new materials including carbon nanotubes, graphene, and molybdenum disulfide (MoS2)
  • Performance boosters using III-V channel materials in CMOS devices
  • Random-variation-robust devices and circuits
  • Novel device simulation and modeling as CMOS extension technology
  • Device-circuit cooptimization technique as CMOS extension techniques
  • Application and development of new nanoscale electronic devices (e.g., graphene, single electron transistor) and MEMS/NEMS-based devices

Before submission authors should carefully read over the journal’s Author Guidelines, which are located at http://www.hindawi.com/journals/jece/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/submit/journals/jece/circuits.systems/cmos/ according to the following timetable:

Manuscript DueFriday, 15 August 2014
First Round of ReviewsFriday, 7 November 2014
Publication DateFriday, 2 January 2015

Lead Guest Editor

  • Changhwan Shin, School of Electrical and Computer Engineering, University of Seoul, Seoul 130-743, Korea

Guest Editors

  • Hyun-Yong Yu, School of Electrical Engineering, Korea University, Seoul 136-701, Korea
  • Youngki Yoon, Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada
  • Donovan Lee, SuVolta, Inc. Los Gatos, CA, USA