ESL (electronic system-level) design is an emerging design methodology that allows designers to work at higher levels of abstraction than typically supported by register transfer level (RTL) descriptions. Its growth has been driven by the continuing complexity of IC design, the shortening time to market, and growing number of design constraints and objectives, which have made RTL implementation less efficient.

ESL methodology holds the promise of dramatically improving design productivity by accepting designs written in high-level languages such as C, SystemC, C++, and MATLAB, and implementing the function straight into hardware. Designers can also leverage ESL to optimize performance and power by converting compute intensive functions into customized cores in SoC designs or FPGAs. It can also support early embedded software development, architectural modeling, and functional verification.

ESL has been predicted to grow in both user base and revenue steadily in the coming decade. Meanwhile, the design challenges in ESL remain. Some important research challenges include effective hardware/software partitioning and codesign, high-quality high-level synthesis, seamless system IP integration, accurate and fast performance/power modeling, and efficient debugging and verification. Potential topics include, but are not limited to:

• New algorithmic development for high-level synthesis
• Domain-specific high-level synthesis (DSP, processor-based, control-intensive, etc.)
• High-level synthesis for emerging technologies (3D, biochips, nanoscale circuits, etc.)
• Extensible/reconfigurable processor synthesis
• ESL design space exploration
• Virtual prototyping
• Transaction Level Modeling
• Hardware/software partitioning and codesign
• Hardware/software interaction and interface
• ESL-to-RTL verification
• ESL debugging
• ESL power/performance analysis
• ESL-IP integration
• ESL for FPGAs
• ESL and embedded-software development
• Design case studies with ESL

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