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Journal of Nanomaterials
Volume 2012 (2012), Article ID 724121, 7 pages
http://dx.doi.org/10.1155/2012/724121
Research Article

Improving the RF Performance of Carbon Nanotube Field Effect Transistor

Faculty of Sciences I, Lebanese University, Beirut, Lebanon

Received 27 September 2011; Accepted 9 February 2012

Academic Editor: Teng Li

Copyright © 2012 S. Hamieh. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

1. Introduction

Carbon nanotubes belong to the fullerenes family and are sheets of graphite rolled in the shape of a tube. Depending on the direction in which the nanotubes are rolled (chirality), they can be either metallic or semiconducting [1]. Semiconducting nanotubes have been used in high-performance transistors where the channel is the nanotube itself. Since the first demonstration of carbon nanotube field-effect transistors (CNTFETs) in 1998 [2, 3], there has been an immense research concerning the electrical properties and the physical understanding of CNTFET [1, 4, 5]. The manufacturing of CNTFET processes progress continually: one of the most advanced is the chemical vapor deposition technique (CVD). The CNTFET can be characterized by high carrier mobility, low leakage current, important on state current relatively to the applied voltages, and low inverse subthreshold slope. These properties allow us to consider the design of high-speed and high-performance electronic circuits. High-performance CNTFET operating close to the ballistic limit has been reported in [68]. However, due to the large size of the probe pads relative to the CNT device, the parasitic capacitance of the pads can dominate the measured frequency response and inhibit measurement of the intrinsic response of CNT transistors. Moreover, the low current drive and high-input/output impedance of single CNTFET make it difficult to perform direct measurements of high-frequency electrical properties using instrumentation based on a reference impedance of 50 Ω. In order to make a direct measurement of a recognized high-frequency figure of merit, such as 𝑓𝑇 small signal 𝑆-parameter measurements were achieved by a newly developed multiple-channel CNTFET structure whose output impedance is much lower than the usual single-channel CNTFET and a deembedding scheme that removes existing errors in measured 𝑆-parameters [9]. The authors of [9] measure 𝑓𝑇=10.3GHz after de-embedding. More recently, using one individual 100 μm long single-walled carbon nanotube, 100 individual nanotube top-gated field effect transistors are combined in a finger geometry to produce a single transistor with a cutoff frequency (after deembedding parasitic capacitance of the finger structure) of 7.6 GHz; before deembedding the cutoff frequency is 0.2 GHz [10].

In this work, we use compact model, in a quasi-static approach simulations to examine the high-frequency performance potential for a state-of-the-art CNTFET. Using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance. The results presented here should prove useful for understanding and optimizing high-frequency characteristics of CNTFET and assessing the potential of CNTFET for nanoelectronic RF applications.

This paper is organized as follows. In Section 2, the compact model is presented. In Section 3, the results of our model using VHDL-AMS simulator in the quasistatic approach are shown and discussed. In Section 4 a new architecture is proposed and the results of the proposed architecture are presented. The conclusions are summarized in Section 5.

2. Approach

A simple model for ballistic nanotransitors is described in [11, 12]. For details about this model, we refer the reader to [1315]. In this model, the gate voltage 𝑉gs induces charge in the CNTFET channel 𝑄cnt. It also modulates the top of the energy band between the source and the drain by an amount 𝑉cnt. As the source-drain barrier is lowered, current flows between the source and the drain. The electrons coming from the source fill +𝑘 states and the electrons coming from the drain fill up the 𝑘 states. The control potential 𝑉cnt is computed self consistently using𝑉cnt=LC𝐼𝑉gi+𝐶SE𝑉si+𝐶DE𝑉di𝑄cntLC𝐼+𝐶DE+𝐶SE,(1) where 𝑉gi, 𝑉si, and 𝑉di are the intrinsic gate, source, and drain potential respectively. 𝐶SE, and 𝐶DEare the contact capacitance of the source and drain, 𝐶𝐼, is the gate oxide capacitance (see Table 1), 𝑄cnt depends on the number of carriers in the channel 𝑛cnt which is the sum of the energy subband contributions, and 𝐿 is the nanotube length. The drain current equation is derived from the Landauer formula which describes ballistic transport with ideal contacts:𝐼=4𝑒𝑘𝐵𝑇𝑝ln1+exp𝑉siΔ𝑝+𝑉cnt𝑘𝐵𝑇ln1+exp𝑉diΔ𝑝+𝑉cnt𝑘𝐵𝑇,(2) where Δ𝑝 is the minima of the 𝑝th energy subband. The sub-bands minima can be calculated using zone folding method of the graphene electron dispersion:𝜖𝜈(𝐤)=𝜖graphene||𝐤||𝐊𝟐||𝐊𝟐||+𝜈𝐊𝟏(3) with𝑁𝜈=2𝑁+1,,2,𝜋||𝐓||<||𝐤||<𝜋||𝐓||,(4) where |𝐓| is the unit vector for the carbon nanotube (CNT), 𝑁 is the number of hexagons in CNT unit cell, and 𝐊𝟏 and 𝐊𝟐 define the CNT reciprocal unit cell [16].

tab1
Table 1: CNTFET parameters (see text for discussion about the used values of the parameters).

3. Quasistatic Approach and Results of Simulation

In the quasistatic approach to transistor modeling, dynamic behavior is predicted by employing static equations for charge (or carrier density) and transport current, but with static voltages replaced by their time-dependent counterparts:𝑄𝑉𝐺,𝑉𝐷,𝑉𝑆𝑉𝑄𝐺(𝑡),𝑉𝐷(𝑡),𝑉𝑆𝐼𝑉(𝑡),𝐺,𝑉𝐷,𝑉𝑆𝑉𝐼𝐺(𝑡),𝑉𝐷(𝑡),𝑉𝑆(𝑡),(5) where 𝑄 is charge, 𝐼 is current, 𝑡 is time, and 𝑉𝐺, 𝑉𝐷, and 𝑉𝑆 are the gate, drain, and source voltages, respectively. Employing the model presented in the last section with the quasistatic assumption, one can determine the ac behavior of CNTFET. The standard procedure is to assume sinusoidal excitation, write each time-dependent quantity in (5) in terms of static (dc or bias) and dynamic (ac, or small-signal) parts, for example, 𝑉(𝑡)=𝑉𝑐+𝑉𝑎exp(𝑗𝑤𝑡) where 𝑉𝑐 refers to the dc value and 𝑉𝑎 refers to the complex ac amplitude, and then make simulation to solve the equations for the ac terminal currents in terms of the ac terminal voltages.

3.1. VHDL-AMS Implementation

The MOSFET-like CNTFET compact model introduced in last section using the quasistatic approach is implemented with VHDL-AMS simulation tool. The main quantities used in the model are the control potential 𝑉cnt, the subbands energy level Δ𝑝, and the source (drain) Fermi level 𝜇𝑆(𝐷). A maximum of 12 intrinsic parameters are necessary as input of this model: the chirality vector (𝑛,𝑚), the diameter, the flatband voltage 𝑉FB, the contact resistances (𝑅𝑠,𝑅𝑑,𝑅𝑔), the contact drain (source) capacitance 𝐶DE (𝐶SE), and the gate oxide capacitance per unit length 𝐶𝐼. (The values of the parameters shown in Table 1 are estimated under the assumption that the compact model results for 𝐼-𝑉 characteristics should be compatible with the results of the model based on Boltzmann transport equation.) The value of 𝐶𝐼 can be calculated from, 𝐶𝐼=2𝜋𝜖0𝜖𝑜𝑥/((2+𝑑)/𝑑), for a nanotube surrounded by a coaxial gate, both separated by an oxide of thickness with permittivity 𝜖𝑜𝑥. The device parameters used in the simulation for the 𝐼-𝑉 characteristics are summarized in Table 1. In Figure 1, we show the results of simulation based on our model for the intrinsic 𝐹𝑇 as function of 𝐼ds for 𝑉ds=100mV (solid line), 𝑉ds=225mV (dotted line), and 𝑉ds=350mV (dashed line). The variation of 𝐹𝑇 with 𝐼ds, which is apparent in Figure 1, can be divided into three regions. region 𝐼 is the low current region where 𝐹𝑇 decreases as 𝐼ds decreases, region 𝐼𝐼 is midcurrent region where 𝐹𝑇 is approximately constant, and region 𝐼𝐼𝐼 is the high-current region where 𝐹𝑇 decreases as 𝐼ds increases. The reasons for this behavior of 𝐹𝑇 with 𝐼ds can be appreciated by plotting 𝐼ds as function of 𝑉gs at constant 𝑉ds where 𝑔𝑚=𝜕𝐼ds/𝜕𝑉gs|𝑉ds is zero in the high-current region. The results of the simulation are very promising: the maximum obtained value of 𝑓𝑇450GHz. However, if the extrinsic parasitic capacitance was included the RF performance of the carbon nanotube transistor will be reduced significantly. This will be our goal in the next section where we propose a new architecture to improve the performance of the CNTFET in the RF regime.

724121.fig.001
Figure 1: Intrinsic 𝑓𝑇 as function of 𝐼ds for 𝑉ds=100mV (solid line), 𝑉ds=225mV (dotted line), and 𝑉ds=350mV (dashed line).

4. Multifinger Multitube Field-Effect Transistors

In this section, a new architecture “multifinger multitube field-effect transistor” (MMFET) is proposed that expected to increase the performance of the nanotube in high-frequency applications [10]. In the proposed architecture, using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance. Shown in Figure 2 a schematic indication of the MMFET geometry (not to scale). In total, there are 16 tubes and 25 fingers (gate) in our design. The distance between two nanotubes is taken to be 2𝑑 [17]. In the next two subsection we will study the DC performance and dispersion of this new architecture, and in the last two subsections, we will study the RF performance and applications of such architecture in RF circuits like ring oscillator.

724121.fig.002
Figure 2: Schematic indication of MMFET device geometry (not to scale). In total, there are 16 tubes and 25 fingers (gates) in our design.
4.1. DC Performance of MMFET

Figure 3 shows the simulated 𝐼ds-𝑉ds characteristic for constant 𝑉gs (see figure) at room temperature of our device. The device parameters used in the simulation are summarized in Table 1. The simulation has taken into account the series resistances. As one can expect, the current found for MMFET is 400× the single CNTFET current for the same characteristics.

724121.fig.003
Figure 3: 𝐼ds-𝑉ds for the (19,0) CNTFET (color online).
4.2. Dispersion

Many physical parameters values vary in a wide range when nanotubes are manufactured. The most important impact is due to diameter dispersion. Here we will study the impact of the dispersion on the obtained diameters based on chirality vectors. The simulation is done using the following steps.(1)Find all chirality vectors (𝑚,𝑛) which produce a diameter between 1.2nm and 1.8nm.(2)Eliminate those vectors that give a metallic nanotube. 22 chirality vectors are found after elimination.(3)Generate a uniform random number to pick up 16 chirality vectors out of the 22 chirality vectors. (Note that, the 16 chirality vectors correspond to the 16 nanotubes used in our simulation in the new architecture.)(4)Generate another uniform random numbers for each trial.

In Figure 4, we show the minimum sub-band energy of the nanotube versus tube diameter for each chirality vector. The impact of the diameter dispersion on the 𝐼ds-𝑉gs characteristic at 𝑉ds=800mV is shown in Figure 5. According to the results shown in Figure 5, we can conclude that the 𝐼on/𝐼off ratio is very sensitive to diameter spreading. To see the distribution of 𝐼ds for fixed 𝑉ds=0.8 V, we show the current versus number of events that fall within 𝐼ds and 𝐼ds±Δ𝐼ds with Δ𝐼ds=0.2mA. This distribution, as one can expect, can be compared to gaussian distribution with, in this case, a mean value 𝐼meands3.4mA and 𝜎0.21mA. Figure 6 shows the number of trial versus the current at 𝑉ds=800 mV.

724121.fig.004
Figure 4: Minimum of the nanotube energy subband versus tube diameter.
724121.fig.005
Figure 5: Impact of the diameter dispersion on the 𝐼ds-𝑉gs characteristic at 𝑉ds=800mV.
724121.fig.006
Figure 6: The number of trial versus the current at 𝑉ds=800mV.
4.3. RF Response with Parasitic Capacitance of MMFET

From Section 3 we conclude that intrinsic device delay metric of CNTFET has high performance. However, from a circuit/system perspective, a realistic scenario should incorporate all the necessary parasitics. For the sake of comparison, we have studied the MMFET device with same characteristics as Si MOSFETs of the 65 nm technology. The parasitic capacitance per nanotube 𝐶tube (𝐶tube is the capacitance added when a one nanotube is added to our device) between the gate and the source (drain) electrode is computed using Fastcap [18]. The thickness of the Pd source (drain) film is 100 nm thick and 60 nm of length, the gate insulator Al2O3 thickness is 65 nm with dielectric constant ~9, and the Al gate is 150 nm thick and 140 nm length. It is assumed that each nanotube introduces a 4 nm width. Using Fastcap, with the geometries shown in Figure 7, we obtain 𝐶tube0.1fF. In Figure 10 we show the discretization used in Fastcap for the geometries that we proposed. (For the sake of clearness we give details on the simulation of the capacitor by Fastcap:(i)we generate two cuboid with cubegen; (ii)the generated objects are combined in a list were we define their position with respect to each other and the dielectric material; (iii)we run Fastcap on the 𝑙st file with the option 𝑙. To produce a picture of the capacitor the 𝑚 option should be used.)

724121.fig.007
Figure 7: The used geometries for calculating the parasitic capacitance per nanotube 𝐶tube in the MMFET.

In this simulation, we have used the measured parasitic capacitance for the multifinger device found in [10] as our initial value 𝐶exp50fF, and for each nanotube we have introduced 𝐶tube in such way:𝐶total=𝐶exp+𝑁tube𝑁1nger𝐶tube,(6) where 𝑁tube and 𝑁nger are the number of tubes and fingers in the device, respectively. (With a new technology this value can be reduced significantly.)

In Figure 8, we show the results of simulation based on our model for the 𝐹𝑇 as function of 𝐼ds for 𝑉ds=400mV: the intrinsic 𝐹𝑇/100 (solid line), and from top down extrinsic MMFET where the number of nanotube change from 16 to 2 by step of 2. The device parameters used in this simulation are summarized in Table 2. As expected, the MMFET device that we propose improves the performance of the carbon nanotube in the RF regime where we found the maximum extrinsic 𝐹ex𝑇6GHz (see Figure 9) and the maximum intrinsic 𝐹in𝑇800GHz value that has to be compared to the maximal measured value 𝐹in𝑇10.2GHz [9].

tab2
Table 2: CNTFET parameters.
724121.fig.008
Figure 8: RF response with parasitic capacitance of MMFET at 𝑉ds=400mV: from top down the number of nanotube changes from 16 to 2 by step of 2. Intrinsic 𝐹𝑇/100 solid line. Same parameters as CMOS 65 nm technology are used (see text).
724121.fig.009
Figure 9: The maximum value of extrinsic 𝐹𝑇 of the MMFET at 𝑉ds=400mV versus number of nanotubes, 𝑛tube.
724121.fig.0010
Figure 10: Discretization used in Fastcap.
4.4. Ring Oscillator with Carbon Nanotube

The parasitic capacitors play important role in the delay characteristics of a MMFET-based circuit. Simulations have been done with a three-stage ring oscillator (see Figures 11 and 12) and the effect of these parasitics has been studied. Figure 13 shows the effect on the natural oscillation frequency of parasitic capacitors with the parameters summarized in Table 2. (Of course the parasitic capacitance is not taken from Table 2.) It can be concluded from Figure 13 that in the range studied here, the parasitics dominate the performance. It should be noted, however, that the accurate estimation of the parasitics would be possible only when the layout geometry and a fabrication process of the MMFETs will be known. Further, it is worthwhile to mention that, for long channel MMFET under high bias, the effects of scattering with phonon are important and have to be considered.

724121.fig.0011
Figure 11: Three-stage ring oscillator.
724121.fig.0012
Figure 12: Schematic representation of a single inverter with 𝑉+=0.4V and 𝑉=0.4 V.
724121.fig.0013
Figure 13: Natural oscillation frequency as function of 𝐶para under ballistic transport.

5. Conclusions

This paper use circuit-compatible modeling technique for the ballistic CNTFET for applications to radio frequency circuits. Results of simulation for radio frequency circuits using VHDL-AMS simulator in the intrinsic case are presented. A new architecture was proposed to improve the performance of the CNTFET. We found that the extrinsic 𝐹𝑇 and the natural oscillation frequency of a three-stage ring oscillator are ~10 Ghz in the cases considered here. An experimental validation for the obtained results is necessary. From our analysis on the high-frequency performance of CNTFET, we conclude the following. (i)Classical lithography reproduces the same problem as CMOS. To overcome this problem we propose a metallic nanotube contacts. (ii)Effect of phonon scattering can be important and have to be considered in the RF regime.(iii)Non-quasistatic effects may not be very important.

We hope to address some of these issues in the near future.

Acknowledgment

The authors would like to thank the support of this work by the Institut TELECOM under NanoRF project.

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