- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Annual Issues ·
- Article Processing Charges ·
- Articles in Press ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Journal of Nanomaterials
Volume 2013 (2013), Article ID 195325, 17 pages
Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM
Faculty of Engineering, Multimedia University, Persiaran Multimedia, 63100 Cyberjaya, Selangor, Malaysia
Received 30 April 2013; Accepted 11 July 2013
Academic Editor: Ugur Serincan
Copyright © 2013 Meng Chuan Lee and Hin Yong Wong. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order to meet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run into many critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.
Charge storage nonvolatile memory (NVM), that is, standard floating gate (FG) and nitride-based charge trap flash (CTF) memory, has always been at the heart of the evolution of IT mobile devices, for example, tablet, cell phone, digital camera, and so forth. The future outlook of charge storage NVM is getting brighter as the world’s technological per-capita capacity to store information has roughly doubled every year and projected to create up to 2.5 quintillion bytes of data everyday as of 2012 [1, 2]. This indicates the insatiable demand for bigger storage space, and lower cost per bit continues to rise for flash memory in the future. The persistent effort to achieve bigger memory space at lower cost was driven by Moore’s law of cost reduction through technological scaling [3–6]. Conventional technology scaling that typically scales down the physical dimensions of charge storage NVM came into fruition through the advancement in lithography techniques as the main driving force . As shown in Figure 1, technology trend of charge storage NVM predicted by International Technology Roadmap for Semiconductors (ITRS) 2011 revealed that the floor space of charge storage NVM continues to shrink, and by 2015, flash memory is predicted to be scaled to 16 nm . Beyond 30 nm, this continuous aggressive scaling of charge storage NVM is fast approaching NVM device’s fundamental limit or its practical limit in considering the balance between economic gain and investment required to resolve issues that arise from scaling . Technological scaling of charge storage NVM has unveiled many critical reliability issues related to device characteristics, for example, charge loss (CL), charge gain (CG), and random telegraph noise (RTN) exhibited through threshold voltage () shift and broadening of memory cell, neighboring bit interference (i.e., disturb phenomenon), cell-to-cell coupling interferences, and severe short channel effects.
Increase in cell-to-cell interference and decrease in gate coupling ratio have been highlighted as the two main technology barriers to develop memory technology of sub-40 nm and less [4, 5, 7–14]. Furthermore, technological scaling of physical dimension for memory cell alone will not be able to completely overcome these reliability issues. Kinam et al. have proposed and emphasized that further technology scaling should be complemented with novel mitigation approaches to extend the dominance of charge storage NVM in semiconductor market [4–14]. Many researchers have dedicated their research work on these novel approaches to extend the longevity of charge storage NVM devices beyond 30 nm. These novel approaches include (1) novel flash cell structures [4, 15–19], for example, Hemi-Cylindrical FET (HCFET) and FinFET; (2) new lithography process technologies, for example, improvement in patterning techniques to realize 20 nm structures ; (3) novel materials in charge storage layer, for example, phase change memory (PCM) [21–37], magnetic random access memory (MRAM) , and nanocrystal [38–59]; (4) tunnel barrier engineering, for example, VARIable Oxide Thickness (VARIOT) [60–63], and implementation of high-k dielectric [64, 65], for example, HfO2; (5) enhancement of flash memory system by integrating complex compensation schemes through implementing embedded flash controllers ; (6) improvement made on error correction code (ECC) algorithm ; and (7) innovative way to stack flash cell, for example, high density 3D stack NAND flash and cross point memories. As transistor based charge storage NVM approaching fundamental limits of NVM characteristics soon, these technical solutions or combination of them could be the key in future development of charge storage NVM. Thus, thorough studies and understanding of these technical solutions are required.
This paper is focused on providing comprehensive review on research findings on reliability challenges and technical solutions to mitigate device characteristics issues that stem from technology scaling of charge storage NVM. In Section 2, reliability challenges resulted from technology scaling of charge storage NVM are reviewed. In Section 3, an overview of viable technical solutions is reviewed. These technical solutions consist of tunnel barrier engineering, novel flash cell structures, and emerging NVM technologies that quickly evolve from research phase to production, for example, PCM. Among the technical mitigation methods, three of the mature technical solutions are discussed in detail, that is, tunnel oxide nitridation, nanocrystal memory, and PCM. Based on comprehensive work done by research groups on these three mitigation methods, key advantages and critical reliability challenges are reviewed. Section 4 reviews tunnel oxide nitridation in detail and assesses the intricate changes of implementing top/bottom nitridation to endurance/retention performance of charge storage NVM. In Sections 5 and 6, intricate research findings of emerging NVM technologies, that is, nanocrystal and phase change memory (PCM), are reviewed, respectively. These novel NVM technologies may eclipse standard FG flash memory as the main driving force to sustain the growth of semiconductor market due to its superior scalability. Section 7 wraps up our review. Our thorough review in this paper can be served as good reference to understand recent research findings on the reliability challenges of charge storage NVM that stems from technology scaling and technical solutions (in research phase or in production) to mitigate device characteristic issues of charge storage NVM.
2. Reliability Challenges of Technology Scaling for Charge Storage NVM
To achieve larger memory space with lower cost per bit, relentless cost saving effort was aggressively pursued through reduction in physical dimension of charge storage NVM as shown in Figure 1. Recent publications have reported that further scaling beyond 30 nm has resulted in critical reliability challenges. These challenges on device characteristics of charge storage NVM include cell level instability issues, array level instability issues due to cell-to-cell interference, RTN, and so forth. These mechanisms yielded read failures through broadening and shifting of distribution of memory cells that impact the memory window (MW). Table 1 summarizes crucial reliability challenges faced by charge storage NVM and critical findings based on comprehensive work done by many researchers.
3. Overview of Viable Technical Solutions
Throughout the technology scaling trend of charge storage NVM, there are two main obstacles to breakthrough to reach the next technology nodes, that is, limitation on lithography process and device characteristics (as reviewed in Table 1). Optical lithography techniques have been improved to extend the longevity of optical lithography tools to sub-30 nm . Double patterning techniques or especially self-aligned spacer double patterning (SADP) technique are best suited to develop 20 nm structures to extend 193 nm immersion lithography processes  while anticipating next generation extreme UV (EUV) tools. Furthermore, it has been implemented in volume manufacturing of high density NAND devices. For reliability challenges on device characteristics issues due to technology scaling, the key strategy as proposed by many researchers is to replace conductive floating gate (FG) with compact discrete charge trapping layer [4, 6, 9, 11, 66] to enable further physical dimension scaling of memory cell which is not possible for FG flash memory. To further mitigate the reliability challenges due to technology scaling as reviewed in Table 1, there are many viable technical solutions proposed by researchers to overcome device characteristics issues due to continuous technology scaling. These proposed technical solutions are summarized in Table 2 as shown next.
As shown in Table 2, the viable technical mitigation solutions can be categorized to tunnel barrier engineering (TBE), novel flash cell structure, and emerging NVM technologies. To further enhance the endurance and retention performance of tunnel dielectric of charge storage NVM, TBE was implemented by modulating the electrical properties of tunnel dielectric through several major techniques, that is, (1) nitridation at top/bottom interfaces of tunnel oxide layer [67–82]; (2) implementation of novel VARIOT concept [60–63]; and (3) replacement of conventional oxide layer with high-k dielectric material [64, 65]. Tunnel oxide nitridation is performed by incorporating optimized nitrogen concentration at top/bottom tunnel oxide layer of charge storage layer through thermal nitridation and chemical/physical nitridation process techniques to enhance reliability performance of charge storage NVM devices . Implementation of novel VARIOT concept involves two-layer dielectric stack with a combination of low-k/high-k or three-layer dielectric stack with a combination of low-k/high-k/low-k to regulate tunnel barrier height and achieve enhancement in endurance/retention characteristics of charge storage NVM devices [60–63]. Combinational approaches of tunnel oxide nitridation and bandgap engineering have exhibited excellent endurance performance for NAND flash memory .
In order to enhance the reliability performance and scalability of flash memory, high-k materials are employed to substitute oxide layer of interpoly dielectric stack of FG flash memory or tunnel oxide layer of nitride based CTF and FG flash memory [64, 65]. Novel flash cell structures were proposed by researchers to address the severe short channel effects and scalability of standard FG flash memory. In order to surmount critical reliability challenges in device issues that stem from technology scaling, several exploratory and interesting flash cell structures such as FinFET [16–19, 110] and HCFET  are studied. Kwak et al. have reported that HCFET exhibited excellent enhancement in subthreshold swing and off current when compared to planar type NVM cell structure . Thus, this shows that HCFET provides superior short channel effects over planar type NVM cell structure . On the other hand, another type of cell structure, namely, FinFET, is also actively under study for its superior reliability performance [16–19]. Figure 4 shows the TEM cross section of sub-40 nm Bandgap-Engineered (BE) SONOS NVM devices of (a) near planar and (b) FinFET structure . Implementation of FinFET structure in charge storage NVM devices has shown excellent short channel control characteristics and scalability as compared to planar type cell structure [16–19]. Comparing the near planar structure, FinFET structure shows superior resistance to body effect as well as drain induced barrier lowering (DIBL) effect as a result of the capability of gate control [17, 19]. FinFET structure based NVM exhibited superior memory window (MW) based on post P/E cycled distribution data and good feasibility to implement multilevel cell (MLC) which requires stringent control on distribution width [17, 19]. As shown in Figure 5, Lue et al. have reported that novel buried channel FinFET BE-SONOS NVM exhibited excellent P/E endurance characteristics with no significant MW closure or roll up . However, implementation of complex cell geometry of FinFET structure and program/erase optimization faces several hurdles to overcome which requires greater study before FinFET based NVM technology could roll out from the research lab to be ready for production [17–19].
On the other hand, extensive research effort has been put into understanding and developing exploratory NVM technologies such as PCM, MRAM, nanocrystal, and RRAM into mature technology that is ready for production. Among the various exploratory NVM technologies, several NVM technologies such as PCM, MRAM, and RRAM have been thoroughly researched to enable the transition from charge based NVM technology to noncharge based NVM technology. The research on noncharge based NVM technologies heavily concentrated on the innovation in search of new materials to be applied as new charge storage layer. Even though each of these technical mitigation methods are elucidated separately, but research of combinational mitigation methods is carefully studied for the potential improvements in reliability performance [17–19, 47]. In Sections 4, 5, and 6, each of these three mature technical solutions was reviewed in detail, that is, top/bottom nitridation of tunnel oxide, nanocrystal quantum dot memory, and PCM.
4. Tunnel Oxide Nitridation
Tunnel oxide nitridation has long been a topic of great interest as one of the mitigation methods to enhance the reliability of tunnel oxide. This is of great significance for charge storage NVM when there are many reliability issues that arise due to charge traps generated under high electric field of applied FN-tunneling mechanism as summarized in Table 1. The incorporation of nitrogen into tunnel oxide of charge storage NVM through many nitridation schemes (as shown in Figure 6) can enhance the reliability performance of tunnel oxide of charge storage NVM [67–80]. Major advantages of tunnel oxide nitridation include (1) increase in immunity towards FNstress that translates to larger memory window (MW); (2) increase in resistance towards instability induced by irradiation of high energy particles, such as gamma rays ; and (3) effective barrier to prevent the penetration of boron or any impurities from polysilicon (FG) to tunnel oxide layer [70, 77]. Nonetheless based on the recent published literature, tunnel oxide nitridation induces critical instabilities, for example, quick electron detrapping (QED) and random telegraph signal (RTS) [77, 79].
Based on the published literatures, there are two main nitridation methods, that is, bottom nitridation [67–69, 71–76, 78–80] and top nitridation [70, 77] that will be discussed in this section. Bottom nitridation of tunnel oxide is done by incorporating nitrogen in the oxide located near to the channel of charge storage NVM cell [68, 69, 71–76, 78–80]. This method enhances the endurance characteristics through selective substitution of Si–N bond onto dangling bond of Si–O near to SiO2/Si interface . However, the incorporation of excess Si–N bonds in bulk oxide increases the probability of defect-related breakdown . As shown in Figure 7(a), shift of various tunnel oxynitrides was plotted as a function of program/erase (P/E) cycle counts . It shows that tunnel oxynitrides exhibit wider memory window (MW) as compared to conventional dry oxide after extensive P/E cycling [68, 76] as shown in Figure 7(b). For this improvement in endurance characteristics on tunnel oxynitrides, Kim et al. attributed this to reduction in electron trapping in high nitrogen concentration oxide . Kim et al. also reported that increment in nitrogen content improves endurance characteristics and reduces MW closure, but it increases the probability of defectrelated breakdown which may cause retention issue [68, 77, 79, 80]. Lee et al.  reported that tunnel oxide nitridation yields large quick electron detrapping (QED) and random telegraph noise (RTN) for fresh device due to increment in defect density through incorporation of nitrogen content in tunnel oxide.
On the other hand, top nitridation of tunnel oxide is typically done by forming a silicon oxynitride (SiON) layer between floating gate (FG) and tunnel oxide [70, 77] through rapid thermal nitridation with ammonia (NH3) anneal and decoupled plasma nitridation [70, 77]. Similar tradeoff between endurance and retention performance of nitrided charge storage NVM was reported in a recent study . Figure 8(a) shows the normalized of various top nitridation (TN) profile plotted as a function of P/E cycle count . Evidently, it shows that higher nitrogen concentration in TN profile yields larger which means more charges are trapped. Figure 8(b) shows curves of normalized of different TN profile after P/E cycling and after 32 hours bake at 85°C . After bake, normalized slightly reduces for TN-A and TN-B profile, but normalized exacerbates for maximum concentration of TN-C. Based on this intriguing behavior, Kim et al. suggested that TN layer may introduce deep energy traps, and thus, appropriate nitrogen content in TN-A and TN-B profile could cause fewer charges to detrap. However, further increment in nitrogen concentration causes more charges to be trapped due to increase in defect density. The defect generation may surmount the deep energy trap effect and cause higher shift . Kim et al. have attributed the improvement in endurance and retention characteristics of nitrided oxide layer to the substitution of distorted yet stable Si–O bonds in tunnel oxide layer with relatively stronger Si–N bonds to relieve the interface strain [77, 79, 82].
As a summary, the reliability performance of nitrided tunnel oxide depends heavily on the specific nitridation schemes and distribution of nitrogen concentration with consideration of the tradeoff between endurance and retention behavior [68–82]. Optimal bottom nitridation on SiO2/Si interface does enhance endurance performance while fine-tuned top nitridation on FG/SiO2 can improve retention performance of charge storage NVM. Optimal nitridation process is needed to balance out the tradeoffs and obtain best reliability performance of nitrided NVM devices. The primary advantage of tunnel oxide nitridation is that enhancement in endurance and retention behavior of tunnel oxide can be done by leveraging existing Si material in CMOS compatible fabrication process. This approach yielded cost effectiveness in fabrication. The concern of this approach is that meticulous and precise control in optimal nitridation scheme is required to achieve desired reliability performance of charge storage NVM.
5. Nanocrystal Memory
Discrete silicon nanocrystal NVM was proposed by Tiwari et al. in 1995 [38, 39] as a potential alternative to standard FG flash memory [38–59] as remedy to conflicting requirements of tunnel oxide that stems from incessant technology scaling. To improve program/erase speed and reduce operating voltage, thinner tunnel oxide of FG flash memory is desirable to allow fast and efficient transfer of charges in and out of FG. At the same time, the tunnel oxide isolation between FG and silicon substrate has to be sufficient to meet data retention criterion of 10 years typical for industrial applications. Thus with discrete nanocrystal NVM as alternative, scaling of tunnel dielectric is feasible to achieve lower operating voltage, faster program/erase/read speed, and desirable charge retention time. As comprehensively reported by Chang et al. in , the most common techniques to form nanocrystals as quantum storage dots are self-assembly, precipitation, and chemical reaction. Among these three techniques, precipitation and chemical reaction are found to be more robust in controlling the size and density of nanocrystals .
As shown in Figure 9, silicon nanocrystal NVM replaces conductive polysilicon floating gate charge storage layer of standard flash memory with discrete and mutually isolated charge storage nodes in silicon nanocrystals distributed in control oxide layer [38–41]. Each nanocrystal or “dot” stores few electrons in the control oxide layer, and collectively, these charges will modulate the channel conduction of each memory cell. Due to the nature of distributed discrete charge storage, nanocrystal NVM exhibits excellent inherent immunity towards defects assisted charge leakage through defects in tunnel oxide that critically limits the scaling of tunnel oxide below 8 nm for standard FG flash memory [103–107]. Thus, tunnel oxide of silicon nanocrystal can be further scaled down below 8 nm with consideration for the tradeoff between operating voltage, speed, and charge retention time.
The recent published literature have shown popular trend in implementing combinations of technical mitigation methods as illustrated in Table 2 to better achieve program/erase characteristics and enhance retention performance in the form of larger memory window (MW). As reported by Qian et al., nitridation was performed on silicon nanocrystals as shown in Figure 10 . This approach yielded larger MW, faster programming speed, and improved retention performance . Typical quantum dots used in nanocrystal NVM are based on silicon material, but metal nanocrystals, that is, germanium, Au, Gd2O3, and other refractory metals, are also proposed and researched [40, 47, 56–58]. For better endurance and retention performance as compared to conventional silicon nanocrystal NVM, Kim et al. reported that SiGe dots with HfO2 as tunnel dielectric exhibited desirable balance of low voltage operations and good endurance/retention performance as compared to SiGe dots with conventional SiO2 as tunnel dielectric . On the other hand, Wang et al. reported the use of Au and Gd2O3 nanocrystals based NVM which exhibited ultrafast program/erase characteristics, disturb-free behavior and multilevel cells capability . For typical multilevel cells, disturb-free behavior is critical to clearly distinguish levels of all bits in the same NVM cell. As shown in Figure 11, Lin and Chien reported that HfO2 based nanocrystals NVM exhibited better P/E characteristics and retention performance as compared to conventional FG based NVM . However due to the complexity process implementing these proposed novel combinational approaches, manufacturability of these nanocrystals NVM devices in production environment is still a huge challenge to overcome.
Uniform charge injection mechanisms were used to transport charges into and out from nanocrystals, such as direct tunneling [38–41]. Band diagrams during charge injection, retention and removal are shown in Figures 9(b), 9(c), and 9(d), respectively [38, 39]. The dynamics of charge transport and retention mainly depend on quantum confinement effect and coulomb blockade effect [38, 39, 43]. When an electron is injected and retained in nanocrystal, the nanocrystal is charged up by with representing the nanocrystal capacitance that depends on its size, thickness of tunnel oxide, and thickness of control oxide layer [38, 39, 43]. The charged-up nanocrystal will hence reduces the electric field across the tunnel oxide which then reduces the tunneling current density during program operation . She and King reported that this coulomb blockade effect has its pros and cons . The salient advantage of this coulomb blockade effect is its effectiveness to impede electrons to tunnel through at low electric field (low gate voltage), and this effectively enhances the immunity of nanocrystal NVM towards flash memory disturb . However, coulomb blockade effect negatively impacts programming speed and retention time . To improve programming speed, larger nanocrystals are desirable to achieve fast and high tunneling current during programming operation. Since the nanocrystals are charged up after programming operation, there is significant tendency for the electrons in the nanocrystals to tunnel back to channel. She and King also reported that quantum confinement energy becomes significant because the dimensions of nanocrystals are in nanometer range . Thus, this causes the conduction band of nanocrystal to shift upwards while the conduction band offset between nanocrystal and surrounding control oxide layer reduces . Careful considerations of coulomb blockade effect, quantum confinement effect, and typical 10 years data retention requirement are required to determine the size and density of nanocrystals and the thickness of tunnel oxide. Furthermore, based on TCAD simulations done on nanocrystals, Gasperin et al. reported that width, number, size, and positions of nanocrystals can impact the charge localizations of nanocrystal memory cells which then impact the program window in subthreshold as well as linear region .
As compared to conventional charge storage NVM, for example, standard FG flash memory and nitride based CTF NVM, there are two potential leakage paths, that is, vertical leakage path through intrinsic direct tunneling (DT) and extrinsic defect assisted tunneling of SILC as shown in Figure 12. Based on comprehensive modeling work done by Monzio Compagnoni et al. in , retention time was modeled and calculated as a function of nanocrystal spacing. As shown in Figure 13, direct tunneling (DT) becomes dominant discharge mechanism for large while LT dominates at smaller region below . Monzio Compagnoni et al. reported that minimum of 3.7 nm is sufficient to fulfill 10 years data retention requirement . Therefore, larger spacing between nanocrystals is able to effectively suppress lateral tunneling and improves data retention performance [42, 49, 53]. For nanocrystals with typical diameter of 6 nm and density of cm−2, Monzio Compagnoni et al. reported that minimum tunnel oxide thickness of 4.2 nm is required to fulfill 10 years data retention requirement [45, 53]. As a summary, Tables 3(a) and 3(b) summarize the salient advantages and critical challenges of typical nanocrystal NVM as compared to standard FG flash memory with the corresponding literature references.
6. Phase Change Memory (PCM)
Phase change memory (PCM) or also known as ovonic unified memory is one of the promising emerging NVM that has been developed for the past 10 to 15 years and made it into production. Furthermore, PCM emerges as one of the mature mitigation alternatives to conventional charge storage NVM. PCM primarily depends on the characteristic of chalcogenide material to switch to amorphous or crystalline phases through heat controlled by amplitude and timing of electric pulses in a typical PCM memory array . The most common chalcogenide material used in PCM is Ge2Sb2Te5 (GST) material. In PCM terminology, if GST switches to amorphous state which yielded high resistance, the PCM cell is in reset state. On the other hand, if GST switches to crystalline state which yielded low resistance, the PCM cell is in set state. The difference between set and reset states of chalcogenide material is the atomic order and electron trap density that yielded several order differences in low field resistance [21, 22].
Figure 14(a) shows typical schematic cross section of PCM cell . PCM consists of top/bottom contact, GST layer with “mushroom” shape active region and resistor that acts as “heater” to heat up the active region of GST layer. Figure 14(b) illustrates the electrical current pulse shapes issued during set/reset/read operations . During reset operation, a huge electrical current pulse for a short period of time is issued to melt the active region and convert it from crystalline phase to amorphous phase. On the other hand, during set operation, a moderate electrical current pulse was issued for a sufficient time period to heat up the active region to a distinct temperature between melting and crystalline temperature. This distinct temperature is used to convert the active region of GST material from amorphous phase to crystalline phase. The read operation is done by issuing a small electrical current pulse to measure out the resistance of the PCM cell. The voltage drop across the cell should be lower than the threshold voltage of PCM cell to inhibit destructive read operation that may alter the data content [21, 22].
Figure 15 shows the current-voltage measurement of PCM cell in amorphous and crystalline states during read/set/reset operations . Threshold voltage represents the condition in which the conductivity in amorphous phase changes from high resistance state (or off state) to low resistance state (or dynamic on state) [21, 25]. Below indicated in Figure 15, the resistance of amorphous state is much higher as compared to crystalline state. The amorphous state exhibits electronic threshold voltage switch effect that reduces the resistance of amorphous state to be comparable to crystalline state. This enables set operation to be carried out successfully. Figure 15 also indicates that reset operation of typical PCM cell consumes the most power to melt the active region of GST material. Set operation is the key limit for operating speed of PCM as shown in Figure 14(b).
PCM is one of the production-ready emerging NVM technologies with potential capability of multilevel cell operation as shown in the recent literature. The main attractiveness of PCM is its scalability to sub-20 nm, and recent study has shown that no significant intrinsic retention issue was found on 10 nm technology node . With direct write technology, PCM does not require any erase operation prior to writing data into the memory cell which is similar to DRAM. Fast read/write at low write/read operating voltage coupled with good data retention and superior endurance performance as compared to standard FG flash memory make PCM very attractive in semiconductor industry. Since PCM is chalcogenide based, studies have reported that PCM is immune to charge based radiation effects which is a genuine reliability concern for charge storage NVM. Table 4 summarizes the key attributes of PCM.
Table 5 summarizes recent research findings on reliability issues of PCM. Based on comprehensive work done by Bae et al., physical origins of endurance failures were investigated. There are three types of endurance failures as reported by Bae et al., that is, stuck reset, stuck set, and tail bits with low resistance originating from reset distribution due to composition changes of GST film in active region . Another key challenge of PCM is to ensure that sufficient thermal isolation is placed on the adjacent cells during reset operations to inhibit thermal disturbance effect [27, 28]. Increase in temperature due to thermal disturbance causes reduction in drift and reset resistance [27, 28]. Similar to discrete charge storage NVM, current fluctuations in PCM are impacted by RTN effect . Fugazza et al. have reported that RTN effect on PCM originates from the fluctuation traps located within the amorphous GST material . Since PCM relies on resistance contrast between amorphous and crystalline phases of chalcogenide material, data stability of PCM was reported to depend on structural relaxation process that yielded temperature accelerated time evolution of electrical properties of active region of chalcogenide material. Based on extensive work done by Ielmini et al. and Lavizzari et al., reliability of PCM is mainly attributed to the metastable nature of amorphous phase that can be impacted by structural relaxation process [25, 28]. As a summary, PCM is an excellent mitigation alternative to charge storage NVM that faces imminent steep reliability challenges due to further technological scaling per Moore’s law. Key advantages of PCM are its superior endurance/retention performance, better scalability without significant reliability issues, and immunity towards extrinsic irradiation effects.
In order to quench the insatiable demand for bigger storage space with lower cost per bit, the persistent effort of technology scaling of memory cell dimension has been driven by Moore’s law. However, technology scaling of memory cell dimension alone is not able to surmount the challenges faced by charge storage NVM, especially on device characteristic issues. Further technology scaling is recommended to be complemented with innovative mitigation techniques. In this paper, critical reliability challenges of charge storage NVM with emphasis on device characteristic issues have been reviewed. Overall technical mitigation approaches to overcome fundamental device characteristic issues of charge storage NVM have been discussed. Key advantages and reliability challenges of tunnel oxide nitridation, nanocrystal based NVM, and PCM have been carefully reviewed in this paper. These three mitigation approaches are topics of great interest among researchers to extend the dominance of flash memory in semiconductor NVM industry.
The authors would like to recognize the critical research work done by all research groups.
- IBM, “What is big data?” http://www-01.ibm.com/software/data/bigdata/.
- International Technology Roadmap for Semiconductors, Release, 2011, http://www.itrs.net/home.html.
- G. E. Moore, “Cramming more components onto integrated circuits,” Proceedings of the IEEE, vol. 86, no. 1, pp. 82–85, 1998.
- K. Kim and G. Jeong, “Memory technologies for sub-40 nm node,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '07), pp. 27–30, Washington, DC, USA, December 2007.
- K. Kim, “Future memory technology: challenges and opportunities,” in Proceedings of the International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA '08), pp. 5–9, Hsinchu, Taiwan, April 2008.
- F. Pellizzer and R. Bez, “Non-volatile semiconductor memories for nano-scale technology,” in Proceedings of the 10th IEEE Conference on Nanotechnology (NANO '10), pp. 21–24, Seoul, South Korea, August 2010.
- K. Kim, “Technology challenges for deep-nano semiconductor,” in Proceedings of the IEEE International Memory Workshop (IMW '10), pp. 1–2, Seoul, South Korea, May 2010.
- T.-C. Chen, “Challenges for silicon technology scaling in the Nanoscale Era,” in Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC '09), pp. 1–7, Athens, Greece, September 2009.
- K. Kinam and C. Jungdal, “Future outlook of NAND flash technology for 40 nm node and beyond,” in Proceedings of the 21st IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '06), pp. 9–11, Monterey, Calif, USA, February 2006.
- D. Wellekens and J. Van Houdt, “The future of flash memory: is floating gate technology doomed to lose the race?” in Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT '08), pp. 189–194, Austin, Tex, USA, June 2008.
- K. Kinam, “Memory technologies for 50 nm and beyond,” in Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT '06), pp. 685–688, Shanghai, China, October 2006.
- Y. Koh, “NAND flash scaling beyond 20 nm,” in Proceedings of the IEEE International Memory Workshop (IMW '09), pp. 1–3, Monterey, Calif, USA, May 2009.
- K. Kim, J. H. Choi, J. Choi, and H.-S. Jeong, “The future prospect of nonvolatile memory,” in Proceedings of the IEEE International Symposium on VLSI Technology (VLSI-TSA-TECH '05), pp. 88–94, April 2005.
- K. Prall, “Scaling non-volatile memory below 30 nm,” in Proceedings of the 22nd IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '07), pp. 5–10, Monterey, Calif, USA, August 2007.
- D. Kwak, J. Park, K. Kim et al., “Integration technology of 30 nm generation multi-level NAND flash for 64 Gb NAND flash memory,” in Proceedings of the Symposium on VLSI Technology (VLSIT '07), pp. 12–13, Kyoto, Japan, June 2007.
- P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, “FinFET SONOS flash memory for embedded applications,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 609–612, December 2003.
- T.-H. Hsu, H. T. Lue, Y.-C. King et al., “A high-performance body-tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-type flash memory,” IEEE Electron Device Letters, vol. 28, no. 5, pp. 443–445, 2007.
- H.-T. Lue, Y.-H. Hsiao, P.-Y. Du et al., “A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance,” in Proceedings of the Symposium on VLSI Technology (VLSIT '09), pp. 224–225, June 2009.
- T.-H. Hsu, H.-T. Lue, W.-C. Peng et al., “A study of sub-40 nm FinFET BE-SONOS NAND flash,” in Proceedings of the Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design (NVSMW/ICMTD '08), pp. 115–116, Opio, France, May 2008.
- H. Yaegashi, “The important challenge to optimize the double patterning process toward 22 nm node and beyond,” in Proceedings of the International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA '11), pp. 1–3, Hsinchu, Taiwan, April 2011.
- A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti, and R. Bez, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Transactions on Electron Devices, vol. 51, no. 5, pp. 714–719, 2004.
- K. Kim and S. J. Ahn, “Reliability investigations for manufacturable high density PRAM,” in Proceedings of the 43rd Annual IEEE International Reliability Physics Symposium Proceedings, pp. 157–162, April 2005.
- H.-S. P. Wong, S. Raoux, S. Kim et al., “Phase change memory,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2201–2227, 2010.
- D. Fugazza, D. Ielmini, S. Lavizzari, and A. L. Lacaita, “Random telegraph signal noise in phase change memory devices,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 743–749, Anaheim, Calif, USA, May 2010.
- D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, “Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells-Part I: experimental study,” IEEE Transactions on Electron Devices, vol. 56, no. 5, pp. 1070–1077, 2009.
- S. Lavizzari, D. Ielmini, D. Sharma, and A. L. Lacaita, “Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells-Part II: physics-Based Modeling,” IEEE Transactions on Electron Devices, vol. 56, no. 5, pp. 1078–1085, 2009.
- S. B. Kim, B. Lee, M. Asheghi et al., “Thermal disturbance and its impact on reliability of phase-change memory studied by the Micro-Thermal stage,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 99–103, Anaheim, Calif, USA, May 2010.
- S. Kim, B. Lee, M. Asheghi et al., “Resistance and threshold switching voltage drift behavior in phase-change memory and their temperature dependence at microsecond time scales studied using a micro-thermal stage,” IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 584–592, 2011.
- J. S. Bae, K. M. Hwang, K. H. Park et al., “Investigation on physical origins of endurance failures in PRAM,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '12), pp. EM. 7. 1–EEM. 7. 4, April 2012.
- J. E. Brewer and M. Gill, Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using NVM Devices, Wiley Interscience, Hoboken, NJ, USA, 2008.
- R. Bez, “Chalcogenide PCM: a memory technology for next decade,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, Baltimore, Md, USA, December 2009.
- R. Bez and P. Cappelletti, “Emerging memory technology perspective,” in Proceedings of Technical Program of VLSI Technology, System and Application (VLSI '12), pp. 1–2, 2012.
- G. Servalli, “A 45nm generation phase change memory technology,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, Baltimore, Md, USA, December 2009.
- G. F. Close, U. Frey, J. Morrish et al., “A 256-Mcell phase-change memory chip operating at 2+ bit/cell,” IEEE Transactions on Circuits and Systems, vol. 60, no. 6, pp. 1–13, 2013.
- J. D. Maimon, K. K. Hunt, L. Burcin, and J. Rodgers, “Chalcogenide memory arrays: characterization and radiation effects,” IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 1878–1884, 2003.
- S. Bernacki, K. Hunt, S. Tyson, S. Hudgens, B. Pashmakov, and W. Czubatyj, “Total dose radiation response and high temperature imprint characteristics of chalcogenide based RAM resistor elements,” IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2528–2533, 2000.
- Y. Kwon, D. H. Kang, K. H. Lee, Y. K. Park, and C. H. Chung, “Analysis of intrinsic variation of data retention in phase-change memory using phase-field method,” IEEE Electron Device Letters, vol. 34, no. 3, pp. 411–413, 2013.
- S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbé, and K. Chan, “A silicon nanocrystals based memory,” Applied Physics Letters, vol. 68, no. 10, pp. 1377–1379, 1996.
- S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” in Proceedings of the International Electron Devices Meeting (IEDM '95), pp. 521–524, December 1995.
- T.-C. Chang, F.-Y. Jian, S.-C. Chen, and Y.-T. Tsai, “Developments in nanocrystal memory,” Materials Today, vol. 14, no. 12, pp. 608–615, 2011.
- J. De Blauwe, “Nanocrystal nonvolatile memory devices,” IEEE Transactions on Nanotechnology, vol. 1, no. 1, pp. 72–77, 2002.
- H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory,” IEEE Transactions on Electron Devices, vol. 43, no. 9, pp. 1553–1558, 1996.
- M. She and T.-J. King, “Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance,” IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1934–1940, 2003.
- R. A. Rao, H. P. Gasquet, R. F. Steimle et al., “Influence of silicon nanocrystal size and density on the performance of non-volatile memory arrays,” Solid-State Electronics, vol. 49, no. 11, pp. 1722–1727, 2005.
- C. Monzio Compagnoni, D. Ielmini, A. S. Spinelli, A. L. Lacaita, C. Previtali, and C. Gerardi, “Study of data retention for nanocrystal Flash memories,” in Proceedings of the IEEE International Reliability Physics Symposium Proceedings, pp. 506–512, April 2003.
- K.-M. Chang, “Silicon nanocrystal memory—technology and applications,” in Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT '06), pp. 725–728, Shanghai, China, October 2006.
- X. Y. Qian, K. J. Chen, Y. F. Wang et al., “The role of nitridation of nc-Si dots for improving performance of nc-Si nonvolatile memory,” Journal of Non-Crystalline Solids, vol. 358, no. 17, pp. 2344–2347, 2012.
- B. De Salvo, C. Gerardi, S. Lombardo et al., “How far will Silicon nanocrystals push the scaling limits of NVMs technologies?” in Proceedings of the IEEE International Electron Devices Meeting, pp. 597–600, December 2003.
- D.-W. Kim, T. Kim, and S. K. Banerjee, “Memory characterization of SiGe quantum dot flash memories with HfO2 and SiO2 tunneling dielectrics,” IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1823–1829, 2003.
- R. F. Steimle, R. Rao, M. Sadd et al., “Silicon nanocrystals: from coulomb blockade to memory arrays,” in Proceedings of the 4th IEEE Conference on Nanotechnology, pp. 290–292, August 2004.
- R. F. Steimle, R. Muralidhar, R. Rao et al., “Silicon nanocrystal non-volatile memory for embedded memory scaling,” Microelectronics Reliability, vol. 47, no. 4-5, pp. 585–592, 2007.
- B. De Salvo, C. Gerardi, R. Van Schaijk et al., “Performance and reliability Features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS),” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3, pp. 377–389, 2004.
- C. Monzio Compagnoni, D. Ielmini, A. S. Spinelli et al., “Program/erase dynamics and channel conduction in nanocrystal memories,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 549–552, Washington, DC, USA, December 2003.
- A. Gasperin, E. Amat, M. Porti et al., “Effects of the localization of the charge in nanocrystal memory cells,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2319–2326, 2009.
- A. Cester, N. Wrachien, A. Gasperin, A. Paccagnella, R. Portoghese, and C. Gerardi, “Radiation tolerance of nanocrystal-based flash memory arrays against heavy ion irradiation,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2196–2203, 2007.
- Y.-H. Lin and C.-H. Chien, “Nanoscale 2-bit/cell HfO2 nanocrystal flash memory,” IEEE Transactions on Nanotechnology, vol. 11, no. 2, pp. 412–417, 2012.
- P.-H. Cheng, S.-H. Huang, and F.-M. Wu, “Study of memory performance and electrical characteristics for metal nanocrystal memories,” IEEE Transactions on Nanotechnology, vol. 11, no. 1, pp. 164–171, 2012.
- J. Wang, C. Lin, P. Huang, L. Chang, and C. Lai, “Ultra-fast BNCs with a new multilevel operation,” in Proceedings of the International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA '13), vol. 58, pp. 1–2, 2013.
- S. Gerardin, M. Bagatin, A. Paccagnella, A. Visconti, and E. Greco, “Heavy-ion induced threshold voltage shifts in sub 70-nm charge-trap memory cells,” IEEE Transactions on Nuclear Science, vol. 58, no. 3, pp. 827–833, 2011.
- B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer, “Variot: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices,” IEEE Electron Device Letters, vol. 24, no. 2, pp. 99–101, 2003.
- H.-T. Lue, S.-Y. Wang, E.-K. Lai et al., “BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '05), pp. 547–550, December 2005.
- H.-T. Lue, T.-H. Hsu, S. C. Lai et al., “Scaling evaluation of BE-SONOS NAND flash beyond 20 nm,” in Proceedings of the Symposium on VLSI Technology Digest of Technical Papers (VLSIT '08), pp. 116–117, Honolulu, Hawaii, USA, June 2008.
- S.-Y. Wang, H.-T. Lue, T.-H. Hsu et al., “A high-endurance (>100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 951–955, Anaheim, Calif, USA, May 2010.
- G. Molas, M. Bocquet, E. Vianello et al., “Reliability of charge trapping memories with high-k control dielectrics (Invited Paper),” Microelectronic Engineering, vol. 86, no. 7–9, pp. 1796–1803, 2009.
- L. Larcher and A. Padovani, “High-κ related reliability issues in advanced non-volatile memories,” Microelectronics Reliability, vol. 50, no. 9–11, pp. 1251–1258, 2010.
- S. Lai, “Non-Volatile memory technologies: the quest for ever lower cost,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '08), pp. 1–6, San Francisco, Calif, USA, December 2008.
- E. P. Gusev, H.-C. Lu, E. L. Garfunkel, T. Gustafsson, and M. L. Green, “Growth and characterization of ultrathin nitrided silicon oxide films,” IBM Journal of Research and Development, vol. 43, no. 3, pp. 265–286, 1999.
- J. Kim, J. D. Choi, W. C. Shin et al., “Scaling down of tunnel oxynitride in NAND flash memory: oxynitride selection and reliabilities,” in Proceedings of the 35th Annual IEEE International Reliability Physics Symposium, pp. 12–16, April 1997.
- J.-G. Jee, W. Kwon, W. Lee et al., “Development and optimization of re-oxidized tunnel oxide with nitrogen incorporation for the flash memory applications,” in Proceedings of the 45th Annual IEEE International Reliability Physics Symposium (IRPS '07), pp. 184–189, Phoenix, Ariz, USA, April 2007.
- U. Ganguly, T. Guarini, D. Wellekens et al., “Impact of top-surface tunnel-oxide nitridation on flash memory performance and reliability,” IEEE Electron Device Letters, vol. 31, no. 2, pp. 123–125, 2010.
- S.-Y. Wang, H.-T. Lue, T.-H. Hsu et al., “A high-endurance (>100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 951–955, Anaheim, Calif, USA, May 2010.
- M. Alessandri, C. Clementi, B. Crivelli et al., “Nitridation impact on thin oxide charge trapping,” Microelectronic Engineering, vol. 36, no. 1–4, pp. 211–214, 1997.
- M. Bhat, L. K. Han, D. Wristers, J. Yan, D. L. Kwong, and J. Fulford, “Effects of chemical composition on the electrical properties of NO-nitrided SiO2,” Applied Physics Letters, vol. 66, no. 10, pp. 1225–1227, 1995.
- J. De Blauwe, D. Wellekens, J. Van Houdt et al., “Impact of tunnel-oxide nitridation on endurance and read-disturb characteristics of flash E2PROM devices,” Microelectronic Engineering, vol. 36, no. 1–4, pp. 301–304, 1997.
- H. Fukuda, M. Yasuda, T. Iwabuchi, and S. Ohno, “Novel N2O-oxynitridation technology for forming highly reliable EEPROM tunnel oxide films,” Electron Device Letters, vol. 12, no. 11, pp. 587–589, 1991.
- G. Ghidini, “Charge-related phenomena and reliability of non-volatile memories,” Microelectronics Reliability, vol. 52, no. 9-10, pp. 1876–1882, 2012.
- T. Kim, K. Sarpatwari, S. Koka, and H. Wang, “Comprehensive understanding on the role of tunnel oxide top nitridation for the reliability of nanoscale flash memory,” IEEE Electron Device Letters, vol. 34, no. 3, pp. 396–398, 2013.
- T. Guarini, M. Bevan, M. Ripley et al., “Nitric oxide rapid thermal nitridation for flash memory applications,” in Proceedings of the 18th International Conference on Advanced Thermal Processing of Semiconductors (RTP '10), pp. 166–170, Gainesville, Fla, USA, October 2010.
- T. Kim, D. He, K. Morinville et al., “Tunnel oxide nitridation effect on the evolution of Vt instabilities (RTS/QED) and defect characterization for sub-40-nm flash memory,” IEEE Electron Device Letters, vol. 32, no. 8, pp. 999–1001, 2011.
- W. H. Lee, C.-H. Hur, H.-M. Lee et al., “Post-cycling data retention failure in multilevel NOR flash memory with nitrided tunnel-oxide,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '09), pp. 907–908, Montreal, Canada, April 2009.
- E. V. Jelenković, M. Kovačević, S. Jha, K. Y. Tong, and D. Nikezić, “Defect generation in non-nitrided and nitrided sputtered gate oxides under post-irradiation Fowler-Nordheim constant current stress,” Microelectronic Engineering, vol. 104, pp. 90–94, 2013.
- T. Kim, S. Koka, S. Surthi, and K. Zhuang, “Direct impact of chemical bonding of oxynitride on boron penetration and electrical oxide hardening for nanoscale flash memory,” IEEE Electron Device Letters, vol. 34, no. 3, pp. 405–407, 2013.
- J.-D. Lee, J.-H. Choi, D. Park, and K. Kim, “Effects of Interface Trap Generation and Annihilation on the Data Retention Characteristics of Flash Memory Cells,” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 1, pp. 110–117, 2004.
- Y.-H. Shih, S. C. Lee, H. T. Lue et al., “Highly reliable 2-bit/cell nitride trapping flash memory using a novel array-nitride-sealing (ANS) ONO process,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '05), pp. 551–554, Washington, DC, USA, December 2005.
- N. Mielke, H. Belgal, I. Kalastirsky et al., “Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling,” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3, pp. 335–343, 2004.
- C. M. Compagnoni, C. Miccoli, R. Mottadelli et al., “Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND flash memory arrays,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 604–610, Anaheim, Calif, USA, May 2010.
- W. J. Tsai, S. H. Gu, N. K. Zous et al., “Cause of data retention loss in a nitride-based localized trapping storage flash memory cell,” in Proceedings of the 40th annual IEEE International Relaibility Physics Symposium Proceedings, pp. 34–38, April 2002.
- E. Lusky, Y. Shacham-Diamand, A. Shappir, I. Bloom, G. Cohen, and B. Eitan, “Retention loss characteristics of localized charge-trapping devices,” in Proceedings of the 42nd Annual IEEE International Reliability Physics Symposium Proceedings, pp. 527–530, April 2004.
- A. Furnémont, M. Rosmeulen, K. van der Zanden, J. Van Houdt, K. De Meyer, and H. Maes, “Root cause of charge loss in a nitride-based localized trapping memory cell,” IEEE Transactions on Electron Devices, vol. 54, no. 6, pp. 1351–1359, 2007.
- M. Janai, B. Eitan, A. Shappir, E. Lusky, and G. Cohen, “Data retention reliability model of NROM nonvolatile memory products,” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3, pp. 404–415, 2004.
- M. Janai and M. C. Lee, “Threshold voltage fluctuations in localized charge-trapping nonvolatile memory devices,” IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 596–601, 2012.
- S. Gerardin and A. Paccagnella, “Present and future non-volatile memories for space,” IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3016–3039, 2010.
- S. Gerardin, M. Bagatin, A. Paccagnella et al., “Scaling trends of neutron effects in MLC NAND Flash memories,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 400–406, Anaheim, Calif, USA, May 2010.
- A. Ghetti, C. Monzio Compagnoni, F. Biancardi et al., “Scaling trends for random telegraph noise in deca-nanometer flash memories,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '08), pp. 1–4, San Francisco, Calif, USA, December 2008.
- S. H. Gu, C. W. Li, T. Wang et al., “Read current instability arising from random telegraph noise in localized storage, multi-level SONOS flash memory,” in Proceedings of the International Electron Devices Meeting (IEDM '06), pp. 1–4, San Francisco, Calif, USA, December 2006.
- M. Janai and I. Bloom, “Charge Gain, NBTI, and random telegraph noise in EEPROM flash memory devices,” IEEE Electron Device Letters, vol. 31, no. 9, pp. 1038–1040, 2010.
- N. Shainsky, I. Bloom, Y. Shacham, and B. Eitan, “Read disturb in NROM charge trapping non-volatile memory device,” in Proceedings of the 66th DRC Device Research Conference Digest (DRC '08), pp. 277–278, Santa Barbara, Calif, USA, June 2008.
- Y. W. Chang, G. W. Wu, P. C. Chen et al., “A new interference phenomenon in sub-60nm nitride-based flash memory,” in Proceedings of the 22nd IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '07), pp. 81–82, Monterey, Calif, USA, August 2007.
- Y.-W. Chang, T.-C. Lu, S. Pan, and C.-Y. Lu, “Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 95–97, 2004.
- J.-D. Lee, S.-H. Hur, and J.-D. Choi, “Effects of floating-gate interference on NAND flash memory cell operation,” IEEE Electron Device Letters, vol. 23, no. 5, pp. 264–266, 2002.
- Y. S. Kim, D. J. Lee, C. K. Lee et al., “New scaling limitation of the floating gate cell in NAND Flash Memory,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 599–603, Anaheim, Calif, USA, May 2010.
- S. Joe, M. Jeong, B. Jo, K. Han, S. Park, and J. Lee, “The effect of adjacent bit-line cell interference on random telegraph noise in NAND flash memory cell strings,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp. 3568–3573, 2012.
- D. Ielmini, “Reliability issues and modeling of Flash and post-Flash memory (Invited Paper),” Microelectronic Engineering, vol. 86, no. 7–9, pp. 1870–1875, 2009.
- A. Modelli, F. Gilardoni, D. Ielmini, and A. S. Spinelli, “A new conduction mechanism for the anomalous cells in thin oxide flash EEPROMs,” in Proceedings of the 39th Annual International Reliability Physics Symposium, pp. 61–66, May 2001.
- D. Ielmini, A. S. Spinelli, and A. L. Lacaita, “Recent developments on Flash memory reliability,” Microelectronic Engineering, vol. 80, pp. 321–328, 2005.
- C.-Y. Lu, K.-Y. Hsieh, and R. Liu, “Future challenges of flash memory technologies,” Microelectronic Engineering, vol. 86, no. 3, pp. 283–286, 2009.
- R. Degraeve, F. Schuler, B. Kaczer et al., “Analytical percolation model for predicting anomalous charge loss in flash memories,” IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 1392–1400, 2004.
- C. Zambelli, A. Chimenton, and P. Olivo, “Analysis of edge wordline disturb in multimegabit charge trapping flash NAND arrays,” in Proceedings of the 49th International Reliability Physics Symposium (IRPS '11), pp. MY.4.1–MY.4.5, Monterey, Calif, USA, April 2011.
- A. Spessot, A. Calderoni, P. Fantini et al., “Variability effects on the VT distribution of nanoscale NAND flash memories,” in Proceedings of the IEEE International Reliability Physics Symposium (IRPS '10), pp. 970–974, Anaheim, Calif, USA, May 2010.
- D. Ielmini, F. Nardi, C. Cagli, and A. L. Lacaita, “Size-Dependent Retention Time in NiO-Based Resistive-Switching Memories,” IEEE Electron Device Letters, vol. 31, no. 4, pp. 353–355, 2010.