Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM
Table 1
Overview of major reliability challenges due to technology scaling of charge storage NVM.
Reliability challenges due to technology scaling of charge storage NVM
References
1
Vt distribution broadening and shifting due to cell level Vt instability mechanisms, such as charge loss, charge gain, and RTN. These mechanisms exacerbated along technology scaling
Cell-to-cell coupling interference ratio was found to be inversely proportional to design rules of 2D memory structure that includes FG and charge trap flash (CTF) structures; as shown in Figure 3, 2D memory structure will hit the design limit for coupling interference ratio of 5 at approximately 16 nm