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Figure 4: Simulated drain current as a function of control-gate voltage of a “parallel” nanodot-array device. Parameters are a combination of input-gate voltages and . “1” corresponds to a “high” input voltage (60 mV) and “0” corresponds to a “low” input voltage (0 V). The arrows at A, B, and C correspond to the positions of , where the logic functions of NAND, NOR, and XOR are, respectively, achieved when the current threshold is set to 0.2 nA.