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Journal of Nanomaterials
Volume 2013 (2013), Article ID 702094, 7 pages
http://dx.doi.org/10.1155/2013/702094
Research Article

Multifunctional Logic Gate by Means of Nanodot Array with Different Arrangements

Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan

Received 8 November 2012; Revised 11 February 2013; Accepted 12 February 2013

Academic Editor: Sung Oh Cho

Copyright © 2013 Yasuo Takahashi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. H. Grabert and M. H. Devoret, Single Charge Tunneling, Plenum, New York, NY, USA, 1992.
  2. M. A. Kastner, “Artificial atoms,” Physics Today, vol. 46, pp. 24–31, 1993.
  3. K. K. Likharev, “Single-electron devices and their applications,” Proceedings of the IEEE, vol. 87, no. 4, pp. 606–632, 1999. View at Publisher · View at Google Scholar · View at Scopus
  4. Y. Takahashi, Y. Ono, A. Fujiwara, and H. Inokawa, “Silicon single-electron devices,” Journal of Physics Condensed Matter, vol. 14, no. 39, pp. R995–R1033, 2002. View at Publisher · View at Google Scholar · View at Scopus
  5. Y. Ono, A. Fujiwara, K. Nishiguchi, H. Inokawa, and Y. Takahashi, “Manipulation and detection of single electrons for future information processing,” Journal of Applied Physics, vol. 97, no. 3, Article ID 031101, 19 pages, 2005. View at Publisher · View at Google Scholar · View at Scopus
  6. C. Wasshuber, H. Kosina, and S. Selberherr, “A comparative study of single-electron memories,” IEEE Transactions on Electron Devices, vol. 45, no. 11, pp. 2365–2371, 1998. View at Scopus
  7. T. Kaizawa, T. Oya, M. Arita, Y. Takahashi, and J. B. Choi, “Multifunctional device using nanodot array,” Japanese Journal of Applied Physics, vol. 45, no. 6A, pp. 5317–5321, 2006. View at Publisher · View at Google Scholar · View at Scopus
  8. H. Fukutome, Y. Momiyama, T. Kubo, Y. Tagawa, T. Aoyama, and H. Arimoto, “Direct evaluation of gate line edge roughness impact on extension profiles in sub-50-nm n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2755–2763, 2006. View at Publisher · View at Google Scholar · View at Scopus
  9. T. Skotnicki, J. A. Hutchby, T. J. King, H. S. P. Wong, and F. Boeuf, “The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,” IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16–26, 2005. View at Publisher · View at Google Scholar · View at Scopus
  10. A. Chin and S. P. McAlister, “The power of functional scaling: beyond the power consumption challenge and the scaling roadmap,” IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 27–35, 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara, and K. Murase, “Multigate single-electron transistors and their application to an exclusive-OR gate,” Applied Physics Letters, vol. 77, no. 5, pp. 637–639, 2000. View at Scopus
  12. T. Kaizawa, M. Arita, A. Fujiwara et al., “Single-electron device with si nanodot array and multiple input gates,” IEEE Transactions on Nanotechnology, vol. 8, no. 4, pp. 535–541, 2009. View at Publisher · View at Google Scholar · View at Scopus
  13. Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase, and K. Murase, “Size dependence of the characteristics of si single-electron transistors on SIMOX substrates,” IEEE Transactions on Electron Devices, vol. 43, no. 8, pp. 1213–1217, 1996. View at Scopus
  14. H. Namatsu, Y. Takahashi, K. Yamazaki, T. Yamaguchi, M. Nagase, and K. Kurihara, “Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations,” Journal of Vacuum Science and Technology B, vol. 16, no. 1, pp. 69–76, 1998. View at Scopus
  15. H. Inokawa, A. Fujiwara, and Y. Takahashi, “A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors,” IEEE Transactions on Electron Devices, vol. 50, no. 2, pp. 462–470, 2003. View at Publisher · View at Google Scholar · View at Scopus