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Journal of Nanomaterials
Volume 2013 (2013), Article ID 805361, 6 pages
http://dx.doi.org/10.1155/2013/805361
Research Article

Simulation of an Improved Design for n-Electrode with Holes for Thin-GaN Light-Emitting Diodes

Department of Mechanical Engineering, Taoyuan Innovation Institute of Technology, Jhongli 32091, Taiwan

Received 26 March 2013; Revised 10 June 2013; Accepted 10 June 2013

Academic Editor: Yogendra Mishra

Copyright © 2013 Farn-Shiun Hwu. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A novel design is proposed for n-electrode with holes to be applied in Thin-GaN light-emitting diodes (LEDs). The influence of the n-electrode with holes on the thermal and electrical characteristics of a Thin-GaN LED chip is investigated using a three-dimensional numerical simulation. The variations in current density and temperature distributions in the active layer of n-electrodes both with and without holes are very tiny. The percentages of light output from these holes are 29.8% and 38.5% for cases with 5 μm holes and 10 μm holes, respectively; the side length of the n-electrode (L) is 200 μm. Furthermore, the percentage increases with the size of the n-electrode. Thus, the light output can be increased 2.45 times using the n-electrode with holes design. The wall-plug efficiency (WPE) can also be improved from 2.3% to 5.7%. The most appropriate n-electrode and hole sizes are determined by WPE analysis.

1. Introduction

Light-emitting diodes have many advantages over conventional light sources, such as their narrow spectrum, long lifetime, and good mechanical stability [1, 2]. High-brightness LEDs have been proven to have excellent abilities to function in back and general lighting applications [3]. There are two major methods that can be used to increase the light output of an LED chip: enlarging the area of a single LED chip or manufacturing a monolithic LED chip array [4, 5]. When the area of an LED chip is enlarged, it results in an increase in the input current and the heat dissipation. Several methods have been developed to improve the current distribution and heat transfer in LED chips by means of altering the design of the electrode pattern and the geometry of the structure [69]. The Thin-GaN LED has also been demonstrated to have great potential for high-power illumination usage [8, 1012]. The better current spreading and superior heat dissipation of the Thin-GaN LED allow it to operate under higher power conditions. A better design for the electrode pattern can increase the light-emitting ratio and decrease the thermal burden in the Thin-GaN LED [1]. The current distribution in an LED chip is usually estimated from the light output [8, 10] and is affected by the material properties of the chip, as well as the size and pattern of the electrode [8, 1012]. The current crowding effect can be improved by the insertion of the current blocking layer (CBL) in the epitaxial structure of the Thin-GaN LED [8]. Many different LED chip structures have been designed and fabricated in the search for superior LED performance [1, 4, 8, 13]. Several studies have investigated the fabrication and performance of blue/near-UV LEDs composed of an array of nanowires on a p- or n-GaN thin film substrate [1416]. The problem is that the mass fabrication procedure for LEDs is expensive and time consuming.

Several numerical models have been proposed to explain the phenomenon of current spreading and to find possible ways to obtain better device geometry for LEDs [1, 5, 9, 1719]. Tu et al. improved the design of the n-electrode patterns to obtain more uniform current spreading [1]. Hwang and Shim [20] developed a three-dimensional numerical simulation model, based on the concept of series and parallel connections, with which to investigate current spreading in an LED. The continuity equation for electronic transport can be used in three-dimensional models to simulate the electric potential and current in lateral-injection LED chips. This has proven to be much more economical than other methods [9, 17]. Using this approach, the simulation of complex LED structures becomes possible. The influence of the thermal effect on the performance of the LED has been considered in some studies [8, 10, 11, 13, 20, 21]. In our previous study, a numerical model, which considered the thermal effect, was proposed for simulating a vertical LED chip [22]. The simulation results for different areas of the n-electrode and the influence of CBL were discussed. The results were found to be consistent with the experimental results obtained in the study of Kim et al. [8].

The main problem with Thin-GaN LEDs is the shadowing effect of the n-electrode when current crowding under the n-electrode is serious. Recently, a novel n-electrode with holes has been manufactured with wet etching technology to solve this problem. In the present study, we modify the 3D numerical model developed in our previous work [22] to simulate the influence of the n-electrode with holes. This method is used to investigate the thermal and electrical characteristics of Thin-GaN LED chips operating under high-power conditions. The effects of the hole size are considered. In addition, the wall-plug efficiency (WPE) is also discussed in our numerical model.

2. Numerical Simulation

A Thin-GaN LED chip is analyzed in the present study. A schematic representation of a cross section in the lateral direction is shown in Figure 1. The full chip dimensions are 600 × 600 μm2. The thicknesses of the n-type GaN layer, active layer, and p-type GaN layer are 2.5, 0.07, and 0.07 μm, respectively. A p-type electrode is formed by the application of a 0.93 μm thick Ag/Ni/Au metalized layer to the entire wafer (600 × 600 μm2). The n-type electrode is formed by the application of a 0.7 μm thick Ti/Au metalized layer with various square dimensions and different widths ( = 100, 200, 300, 400, 500, and 600 μm).

805361.fig.001
Figure 1: A cross-sectional schematic representation of a Thin-GaN LED chip in the lateral direction, where represents the size of the n-electrode.

The continuity equation for electronic transport in an LED chip is where is the conductivity and is the electrical potential. The resistivities of the n- and p-type cladding layers are and , respectively; and the other resistivities for the metallic electrode are , , , and . The specific p-contact resistance and the specific n-contact resistance are set to be and , respectively, [8]. Following upon our previous work [22], the current through the active layer is assumed to move in the direction perpendicular to the layer. The equation for calculating the electrical potential in the LED is solved using the finite-element method (FEM). The equivalent conductivity for each element in the active layer is calculated by where is the elemental thickness of the mesh; is the voltage drop between the active layer; and is the elemental current density [23]. The current behavior through the active layer of the LED chip is dominated by the following Shockley equation: where is the saturation current density; is the elementary charge (1.6 × 10−19 coul); is the ideality factor; is the Boltzmann constant (1.38 × 10−23 J/K); and is the absolute temperature [23]. It is well known that and are dependent on the material quality and/or device structure. The parameters used for the geometric dimensions and for the Shockley equation are the same as those used in previous studies [8]: that is, the saturation current and are set to be 4.72 × 10−22 A and 2.5, respectively. The p-pad is set to have a uniform input current and the n-pad is set as the ground. With the exception of the electrodes, the rest of the boundaries in the LED chip are all assumed to be insulated. The relationship between and developed by Millman and Grabel [24] is also adopted in the present study:

The equation for conduction heat transfer with the heat source for the steady-state is where is the thermal conductivity [23]. Based on the law of energy conservation, the input electrical power can be divided into two major parts; one is the light output power and the other is heat generation. Given the same assumptions for the active layer as in (2), we propose the following heat generation term in the active layer [22]: where is the reduced Planck constant;   is the angular frequency; is the internal quantum efficiency at room temperature; and is the light extraction efficiency at room temperature. The heat generated by light absorption inside the LED chip is assumed to be included in this term. In the present study, the value of the external quantum efficiency () is 25%, as obtained in the literature [22]. The heat generation term per unit volume due to Joule heating [23] in the other layers of the LED chip is The thermal conductivities of the materials are summarized in Table 1 [22, 23]. The thermal boundary conditions of the top, lateral, and bottom surfaces of the LED chip are shown by where is the unit normal vector of the interface; is the air temperature; and is the equivalent heat transfer coefficient [23]. A copper slug with a board is usually used to dissipate the heat generated from the LED chip. The size is set to be about 7.2 cm2 in the present study. Natural convection conditions affect the surfaces with and is 300 K. The convection from the bottom surface of the slug is replaced by the convection condition from the chip with the equivalent heat transfer coefficient . In this case, is about .

tab1
Table 1: Thermal conductivities used in the simulation [22, 23].

A self-developed correlation coupling of the thermal and electrical equations is added to the FEM software (COMSOL Multiphysics licensed version 3.4) to obtain the temperature, the electrical potential, and the current density in the LED chip. In the present study, the simulation is performed in a three-dimensional, steady-state condition and the mesh for each layer is made up of triangular prism elements. The mesh numbers for n-electrodes with holes are much higher than for those without holes due to the structure of the holes. After convergence testing, the mesh numbers are found to be 2656, 10681, and 18406 for the cases without holes, with 5 μm holes and with 10 μm holes, respectively, as shown in Figure 2. A circular area 100 μm in diameter is reserved in the central region of the n-electrode for wire bonding. Utilizing a similar testing procedure, the relative tolerance is selected to be 1 × 10−3 for the variables of temperature and voltage.

805361.fig.002
Figure 2: Triangular prism elements of each layer in the LED chip.

3. Results and Discussion

Figure 3 displays the current densities in the active layer for an input current of 100 mA for the cases where μm, without holes, with 5 μm holes, and with 10 μm holes. The simulated current density distributions show almost the same results. In every case, the current crowding beneath the n-electrode is more serious.

805361.fig.003
Figure 3: Current densities in the active layer with an input current of 100 mA for the case of μm.

Figure 4 shows the temperature distribution in the active layer for the cases of μm, without holes, with 5 μm holes, and with 10 μm holes, under the same operating conditions. There is little difference (about 0.1 K) in the maximum temperature in the active layer between the three cases. The temperature distribution results are also the same. Therefore, the structure of the holes on the n-electrode may not cause the change in thermal behavior in the active layer of the LED. The electrical characteristics of the LEDs will not be affected by this slight temperature difference. According to the analyses of the current distribution and temperature distribution, the influences of the n-electrode for cases with and without holes seem very tiny.

805361.fig.004
Figure 4: Temperature distributions in the active layer for the cases with μm.

In order to improve the shadowing effect of the n-electrode, the current density distributions in the active layer, including the shadow of the n-electrode are shown in Figure 5 for different cases. For the case with μm, the area beneath the n-electrode is only 1/9 of the total area in the active layer, but the average current density beneath the n-electrode is 3.78 times that of the rest of the area (see Figure 3). The percentages of the light output power from those holes can be integrated in the present numerical simulation. A comparison between the two cases for n-electrodes with holes of different n-electrode size is shown in Figure 6. The results indicate that the n-electrode with 10 μm holes offers increased light output power, about 2.45 times more than n-electrodes without holes.

805361.fig.005
Figure 5: Current density distributions in the active layer including the shadow of the n-electrode.
805361.fig.006
Figure 6: Percentage of light output with different sizes of n-electrode for the cases with two different hole sizes.

The wall-plug efficiency of the LED chip is defined as the output light power divided by the total input electrical power. Here, the output light power is selected as the electrical power generated by the residual region of the active layer not covered by the n-electrode subtracted from the total heat generated in the same region. The WPEs for different sizes of n-electrodes with 5 μm and 10 μm holes are also discussed, and the results are compared with the cases of n-electrodes without holes, as shown in Figure 7. The welding region occupies most of the area of n-electrodes with 5 μm and 10 μm holes in cases where μm. The n-electrode thus obstructs most light emission for all the cases with and without holes. The WPE for the case without holes is very close to that of the cases with holes. The WPE then decreases as the size of the n-electrode is increased for the cases without holes since the major part of the light emitting area in the active layer is covered by the n-electrode. However, in the cases with holes, the WPE increases when μm and then decreases as the size of the n-electrode increases. The light output from these holes plus that from the residual region of the active layer not covered by the n-electrode equals the total light output. Due to a higher current density under the n-electrode, the WPE for μm reaches a maximum value. Otherwise, the size of the hole will also influence the light output. A larger size will emit more light output. Therefore, a better size for the n-electrode would be μm, in the case with 10 μm holes. The WPE can be increased from 2.33% to 5.72% by the design of n-electrode with holes. Based on the study of nanowire array LEDs [14], these LEDs give an external quantum efficiency of 2.5%. The results of the present study are found to agree with the experimental result obtained in the study of Xu et al. [14].

805361.fig.007
Figure 7: Calculated WPE for different sizes of n-electrode for the cases with and without holes.

4. Conclusions

In the present study, a design is proposed for n-electrode with holes for application in Thin-GaN LEDs. A new numerical model is used to investigate the effect of the n-electrode with holes design on the thermal and electrical characteristics of a Thin-GaN LED chip. The variation in current density and temperature distributions in the active layer is very tiny for n-electrodes with and without holes. The percentage of light output power from these holes ranges from 3.5% to 37.5% and from 3.1% to 49% for the cases with 5 μm and 10 μm holes in n-electrodes with different side lengths (). Therefore, the light output power can be increased 2.45 times by using the n-electrode with holes design. When μm, the wall-plug efficiency for the case without holes is very close to that of the cases with holes. For the cases with holes, the wall-plug efficiency increases when μm and then decreases as the size of the n-electrode is increased. The devices with larger hole size will emit more light output. Thus, the wall-plug efficiency is also improved from 2.3% to 5.7% for the case of μm n-electrodes with 10 μm holes. WPE analysis is used to determine better n-electrode and hole sizes.

Acknowledgment

The authors gratefully acknowledge the support of the National Science Council of Taiwan for this work, through Grant no. NSC 101-2221-E-253-006.

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