Comprehensive Study of Kinetics of Processes Competing during PECVD Ultrathin Silicon Layer High-Temperature Annealing

Figure 7

Oxidation rates (calculated from data shown in Figure 6(b), attributed to the center of each of time slots) during high-temperature annealing for the two types of samples, with “thick” and “thin” PECVD Si layers (full symbols/solid lines and open symbols/dashed lines, respectively).