Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications
Figure 14
(a) Programming and (b) erasing characteristics using FN tunneling of vertical SiNW-based GAA JL-SONOS memory device with channel doping of 1 × 1017 cm−3 and 1 × 1019 cm−3. (Reprinted with permission from [45]. [2011] IEEE.)