Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications
Figure 18
(a) SEM image of a Si nanopillar pattern used for simulating PCE analysis. Pillar parameters are diameter = 200 nm, pitch = 400 nm, and height = 1000 nm; (b) crossectional schematic of axial junction. (Reprinted with permission from [8]. [2010] IEEE.)
