Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 7

Vertical Silicon nanowire TFET process flow schematic. (a) Vertical pillar etch and As implantation to form the drain region, (b) isolation oxide deposition and gate stack formation, (c) the top amorphous-Si etched to expose source side of TFET, (d) source implanted with BF₂, (e) dopant segregated Ni silicidation, (f) contact opening and Al metallization. (Reprinted with permission from [29] [2011] IEEE.)

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