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Journal of Nanotechnology
Volume 2012 (2012), Article ID 943406, 7 pages
Research Article

Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate

1Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran
2Nanotechnology and Quantum Computing Lab., Shahid Beheshti University, G. C., Tehran, Iran
3Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G. C., Tehran, Iran

Received 29 November 2011; Revised 4 January 2012; Accepted 10 January 2012

Academic Editor: Arturo I. Martinez

Copyright © 2012 Razieh Farazkish et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

1. Introduction

Current CMOS technology is going to approach a scaling limitation in deep nanometer technologies. The CMOS technology in nanoscales experienced some problems due to increase in amounts of variation in every aspect of a nanometer design. Quantum-dot cellular automata (QCA) is one of the promising new technologies for future generation ICs that overcome the limitation of CMOS [13]. The fundamental unit of QCA-based design is majority gate; hence, efficient construction of QCA circuits using majority gates has attracted a lot of attention [49].

Since every QCA circuit can be implemented by using only majority and inverter gates, inverter becomes another important component in constructing QCA circuits. Hence, efficiently constructing an inverter in QCA is of great importance [1012].

Fault-tolerant design of QCA logic circuits is absolutely necessary for characterization of defective behavior of QCA circuits. In recent years the fault-tolerance properties of QCA circuits has been demonstrated by many researchers [1317].

As already mentioned, the basic building block of QCA circuit is majority gate; majority logic is a way of implementing digital operations in a manner different from that of Boolean logic. The logic process of majority logic is more sophisticated than that of Boolean logic; consequently, majority logic is more powerful for implementing a given digital function with a smaller number of logic gates [18, 19].

This paper investigates a new design for fault-tolerant majority gate. By applying this new proposed scheme for fault-tolerant majority gate, we can obtain high degree of robustness in terms of misalignment, missing, and dislocation cells. The presented method is justified based on physical proofs as well as simulation results. In comparison to other existing implementations, this majority gate demonstrates significant improvement in terms of area, complexity, and robustness.

One of the most important component in any arithmetic and digital circuits in QCA and VLSI is full adder [47, 2024]. A fault-tolerant QCA full adder can be implemented using the new fault-tolerant majority gate. Improving the robustness of the majority gate cells leads to efficient designing of many arithmetic circuits.

2. Materials and Methods

2.1. Background

Quantum cellular automata is a new device architecture, which is proposed by Lent and Tougaw [25]. A quantum cell can be viewed as a set of four charge containers or dots, positioned at the corner of a square. The cell contains two extra mobile electrons, which can quantum mechanically tunnel between dots but not cells. The electrons are forced to the corner positions by Columbic repulsion. This two possible polarization states represent logic “0” and “1,” as shown in Figure 1(a) [2].

Figure 1: (a) Basic QCA cell and binary encoding, (b) a QCA majority gate, (c) a QCA inverter.

As shown in Figure 1(b), an ordinary QCA gate implementing the majority function is as follows: assuming three inputs labeled A, B, and C, the logic function of majority gate is M(A, B, C) = AB + AC + BC. As illustrated in Figure 1(b) each QCA majority gate requires only five cells. In Figure 1(c) a QCA inverter is shown which simply returns the opposite value that was put in.

2.2. Faults of QCA Circuits

Three major categories of faults can occur during the assembly of a QCA circuit. First, faults may occur when quantum cells are shifted from their intended locations which are called “misalignment” cells. Sometimes misalignment cells have no effect on functionality of a QCA circuit, and also sometimes a misalignment cell may have a polarity opposite what it should. A second type of faults occurs when the quantum cell itself is “missing” resulting in the cell becoming defective. If the gap between ideal cells is large enough, it would have no influence on its neighbors and it can cause a circuit to cease functioning well. A third type of faults occurs when quantum cells are rotated relative to the other cells in the array which is called “dislocation” cells. Also, in this case, the circuit may cease to function (Figure 2).

Figure 2: Faults of majority gate, (a) misalignment cell, (b) missing cell, and (c) dislocation cell.

Based on the researches which have been performed to date, some fault-tolerant QCA circuits have been designed and tested [1416]. But, these circuits are not robust enough to operate correctly when faced with faults. In next section, we have attempted to make a novel fault-tolerant majority gate using physical relation, in such a manner that it can continue to operate correctly in the event of the above-mentioned faults.

2.3. Novel Design for Fault-Tolerant Majority Gate

Majority is a voter. In our new structure, a fault-tolerant majority gate can be implemented as shown in Figure 3. In this scheme we have three inputs labeled A, B, and C and the output cell is shown by out. In addition there are nine middle cells labeled 1, 2, 3, 4, 5, 6, 7, 8, and 9. Polarization of input cells is fixed and middle cells and output cell are free to change.

Figure 3: Proposed fault-tolerant majority gate.

As it is clear in Figure 3, a new fault-tolerant majority gate only needs 13 cells and by considering some physical relations it is implemented.

Regarding the physical proofs, assume that all cells are similar and the length of each one is 𝑎 (𝑎=18 nm) and there is a space of 𝑥 (𝑥=2 nm) between each two neighbors.

In all figures, rectangles show a QCA cell and the circles inside show the electrons within that cell. It should be noted that in order to achieve more stability, electrons of QCA cell are arranged in such a manner that reaches minimum kink energy.

The kink energy between two electron charges is calculated using (1a). In this equation, 𝑈 is kink energy, 𝑘 is fixed colon, 𝑞1 and 𝑞2 are electric charges, and 𝑟 is the distance between two electric charges. By putting the values of 𝑘 and 𝑞, we obtain (1b). 𝑈𝑇 is the summation of kink energies that is calculated from (2) [4, 2628]𝑈𝑘𝑞1𝑞2𝑟,(1a)𝑘𝑞1𝑞2=9109(1.6)21038=23.041029=𝐴=𝑐𝑡𝑒,(1b)𝑈𝑇=2𝑖=1𝑈𝑖.(2)

2.4. Physical Proof

The proposed fault-tolerant majority gate has nine different middle cells, so we should check all the faults that may occur in middle cells to verify the correctness of this scheme. Here, only one of the faults (missing cell 5) is proved and the others can be proved as well. The assumed value of input cells are A = B = 1, C = 0.

First, we calculate the kink energy existing between each electron (𝑒1, 𝑒2, 𝑒3, 𝑒4, 𝑒5, 𝑒6, 𝑒7, 𝑒8, 𝑒9, and 𝑒10) with electrons “𝑥” and “𝑦” in (a) and (b) states using (1a) and (1b) equations. For example, 𝑈𝑖 is the kink energy existing between electrons 𝑒𝑖 and 𝑥 (or 𝑦). Also, 𝑟𝑖 is the distance between two electron charges. Then we calculate the total kink energy (𝑈𝑇) in both states using (2). The comparison of total kink energies in both (a) and (b) states shows which state (a or b) is more stable. We consider the state that has the lower kink energy level as the more suitable one.

As the proof method is similar for all cells and their values and also due to lack of space, only the first part of this proof is stated and the rest of relations are omitted (Figure 4).

Figure 4: (a) The one value in cell 8, (b) the zero value in cell 8.

Figure 4(a) (Electron 𝑥)

Figure 4(a) (Electron 𝑦)
𝑈1=𝐴𝑟1=23.04102943.861090.521020𝑈(𝐽),2=𝐴𝑟2=23.041029401090.581020(𝑈𝐽),3=𝐴𝑟3=23.04102953.741090.431020𝑈(𝐽),4=𝐴𝑟4=23.04102928.281090.811020𝑈(𝐽),5=𝐴𝑟5=23.04102942.941090.541020𝑈(𝐽),6=𝐴𝑟6=23.0410296.631093.481020𝑈(𝐽),7=𝐴𝑟7=23.04102942.051090.551020𝑈(𝐽),8=𝐴𝑟8=23.041029201091.151020𝑈(𝐽),9=𝐴𝑟9=23.04102926.911090.861020(𝑈𝐽),10=𝐴𝑟10=23.041029210911.521020𝑈(𝐽),𝑇12=10𝑖=1𝑈𝑖=20.441020(𝐽).(4) Since cells 1 and 3 are roughly in a long distance from cell 8, their kink energy can be neglected. It should be noted that the value of cell 8 is transferred to the output cell, which give us a majority decision of inputs A, B, and C.

Figure 4(b) (Electron 𝑥)

Figure 4(b) (Electron 𝑦)

With comparison of the achieved results, the electrons in cell 8 are positioned in state (a) which is more stable and has a lower kink energy. It is worth mentioning that in all cells 𝑈𝑇1 is the kink energy in +1 polarization and 𝑈𝑇2 is the kink energy in −1 polarization.

Considering the above computing, we can infer that the proposed structure for implementing a fault-tolerant majority gate is completely correct and resulted in a correct state for the output cell when faults occur.

After physical proof, we can also check the proposed design using QCADesigner. The next section presents the simulation results of this fault-tolerant majority gate.

3. Simulation Results

For the proposed circuit layout and functionality check, a simulation tool for QCA circuits, QCADesigner version 2.0.3 [29], is used. The following parameters are used for a bistable approximation:(i)cell size = 18 nm,(ii) number of samples = 50000,(iii) convergence tolerance = 0.0000100,(iv) radius of effect = 65.000000 nm,(v) relative permittivity = 12.900000,(vi)clockhigh=9.800000𝑒-022 J,(vii)clocklow=3.800000𝑒-023 J,(viii)clock shift = 0,(ix)clock amplitude factor = 2.000000,(x)layer separation = 11.500000,(xi)maximum iterations per sample = 100.

Most of the above-mentioned parameters are default values in QCAD esigner.

Figures 5 and 6 show the simulation results of proposed fault-tolerant majority gate with or without faults. These results are the same as the results of physical proof that was mentioned in previous section.

Figure 5: Simulation results for proposed fault-tolerant majority gate with faults.
Figure 6: Simulation results for proposed fault-tolerant majority gate without faults.

Simulation results reveal that the proposed majority gate is more robust than previous ones.

4. Conclusion

In this paper, we analyzed fault-tolerance properties of the conventional design for majority gate as the based logic gate for implementing QCA circuits. High performance logic component can be achieved by utilizing this fault-tolerant majority gate. We analyzed robustness of proposed majority gate in terms of(i)misalignment cells,(ii)missing cells,(iii)dislocation cells.

Some physical proofs and exhaustive simulation using QCADesigner tool have verified the functionality of this scheme. The presented structure demonstrates significant improvements in terms of area, complexity, and robustness in comparison to previous designs.


The authors would like to thank Dr. Belmond Yoberd for his literature contribution.


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