Abstract
Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecting and is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in ratio for the same drive current.
1. Introduction
While universal scaling trends of CMOS technology are mostly focused on achieving higher speed, selection of device fabrication process parameters for ULP applications with lower operating frequencies is still under exploration [1–5]. It has been shown recently that subthreshold circuits are significantly benefitted by optimizing the device parameters [3]. Process and geometry parameters of superthreshold circuits are largely governed by the different leakage currents and, hence, its static power dissipation [6–10]. However, due to lower supply bias, gate leakage current, DIBL, and punchthrough effects are negligible under subthreshold conditions [11]. Therefore, to some extent, design constraint for selecting and becomes more flexible in case of device operated under subthreshold regime.
For superthreshold devices, scaling of is restricted by the amount of static leakage, mainly subthreshold leakage current in nanometer technology nodes [2, 3]. Such a high device will give significant performance penalty under subthreshold conditions due to lower subthreshold leakage current, which is used to perform necessary digital computations. Hence, the choice of is a tradeoff between speed and leakage power dissipation in case of superthreshold applications. However, in subthreshold region, lower static leakage power dissipation due to scaled even below allows further reduction in to enhance the speed.
Along with subthreshold leakage current, gate leakage is also a major hurdle in aggressive scaling of to obtain better control over the channel for a superthreshold device [2, 3]. In general, scales down slowly from 130 nm technology node to keep minimum gate leakage current in case of high frequency applications [2] due to higher supply bias. However, it degrades “” and causes lowering of ratio. In subthreshold operating region due to lower , reducing will not significantly increase the gate leakage current [11]. In addition, transistor input capacitance is smaller under subthreshold conditions than the superthreshold regime [3]. Hence, more aggressive scaling of is possible under subthreshold conditions to achieve higher speed and lower energy consumption.
In addition, it is an established fact that a superthreshold device in nanometer technology nodes requires halo and retrograde doping to suppress short channel effects. Halo and retrograde wells are used to reduce DIBL and punchthrough effects and to control of the device independent of its subthreshold slope. However, in subthreshold regime, due to supply bias lower than , DIBL and punchthrough effects are negligible. Hence, subthreshold device characteristics are less sensitive to halo and retrograde doping. Therefore, this paper investigates the design of a subthreshold NMOS device at 45 nm technology node with better subthreshold slope and higher drive current capability.
2. Calibration of a MOS Device
Transistors and , as shown in Figure 1, primarily set the transistor performance parameters [12]. Authors in [13] fabricated the optimized 35 nm gate length NMOS device with 676 μA/μm drive current, subthreshold slope = 86 mV/dec., and = 100 nA/μm at = 0.85 V. This device was fully optimized for short channel effect suppression and parasitic resistance reduction. In order to obtain an optimum subthreshold device, there is a need first to design a superthreshold device with better performance at 45 nm technology node. The physical dimensions of a 35 nm NMOS device, fabricated by Toshiba and listed in Table 1, are considered for simulation purposes [13]. The poly-Si thickness is 150 nm, while the distance of S/D contact to gate is 52 nm. In simulation, the source and drain electrodes are treated as ohmic contacts. The resulting SDE junction depth is 15 nm for NMOS and 28 nm for PMOS. Lower for PMOS causes more drive current in PMOS which is comparable to NMOS. Lower in case of PMOS will cause more vertical electric field in channel which further increases subthreshold drive current in PMOS.
Furthermore, channel doping and halo doping are tuned to calibrate our device with the NMOS fabricated in [13] and corresponding electrical characteristics are listed in Table 2. At first, the simulation project matches the published process details of real structure as accurately as possible. It includes the physical parameters as given in Table 1. The calibrated 45 nm device structure, as shown in Figure 2, is obtained with physical parameters as listed in Table 1. The drain current versus gate voltage (-) and drain current versus drain voltage are the primary targets for calibration in device simulations. The calibration starts by adjusting the electrostatic to match subthreshold slope, drain current, and . Finally, device measurements are matched to the previously published calibrated device [13] by doping profiles adjustment so as to achieve the desired - characteristics. The flowchart of the calibration process is given in Figure 3 [14]. For process calibration, tuned mobility parameters are used. The matched calibrated electrical characteristics are then obtained through TCAD simulation. The important figures of merit, extracted from simulation, are then compared with the experimental data in Table 2. This is the starting point for investigating the effect of physical and process parameters under subthreshold conditions.
3. Effect of Oxide Thickness and Channel Length on Device Parameters
As seen in Section 1, one of the key methods to enable gate length scaling over the past several generations is to scale the [15]. Therefore, scaling has been instrumental in controlling short channel effects as MOS gate dimensions have been reduced. This improves the control of the gate electrode over the channel, which enables both shorter channel lengths and higher performance. As scales down, increase in gate leakage current becomes significant below 65 nm technology node as shown in Figure 4. In addition, gate capacitance also increases significantly with scaling for superthreshold circuits. To reduce the increased gate leakage, a gate dielectric with higher dielectric constant is introduced below 45 nm [16]. However, due to lower , gate leakage component is negligible under subthreshold as compared to superthreshold conditions.
The effective gate capacitance of a transistor is dominated by intrinsic depletion and parasitic capacitances, which are strongly dependent on [17]. In energy constraint subthreshold design, circuits are normally optimized to enhance the speed [18, 19]. To reduce these capacitances, higher value of is preferred. However, it reduces the gate control over the channel; hence, it results in higher value of “” Hence, for moderate speed application with some loss of energy, significant improvement in speed can be achieved. In addition, as shown in Figure 5, under subthreshold conditions (), scaling does not increase significantly contrary to superthreshold operating region. The effective channel length also determines subthreshold leakage current and .
Therefore, this section examines the joint impact of and scaling on the device performance. The calibrated NMOS structure, as shown in Figure 2, is simulated to investigate the effect of and on the characteristics of NMOS device under subthreshold conditions at = 150 mV. and are varied from 30 nm to 50 nm and 0.6 nm to 1.3 nm respectively. The values of halo doping and substrate doping are kept constant at /cm3 and /cm3, respectively.
It is observed from Figure 6 that an increase in and a decrease in reduce “” significantly. Increasing from 35 to 50 nm reduces “” by approximately 6 mV/decade for different values of . It is clear from Figure 7 that an increase in channel length has negligible effect on the gate capacitance. Therefore, longer channel length will result in lower power dissipation and better performance because of improved “” Also, reducing from 1 to 0.8 nm at = 35 nm reduces “” by 2.3 mV/decade and increases by 12%. Therefore, careful selection of is required so that the improvement in “” will not be masked by the increase in and hence the power dissipation (f). However, from Figure 7, it is evident that is having large impact on as compared to . In addition, it has been evident that the increase in reduces and current by 14x and 22x, respectively, at = 1 nm. Therefore, ratio increases by 1.36x at =1 nm with the increase in . This also reduces the power consumption. From Figure 8, optimum value of can be obtained for better values of “” and ratio for different values of .
From the above analysis, it can be concluded that, for energy efficient ULP circuits, larger value of can be used to reduce the energy consumption due to lower “” and higher ratio. However, for higher performance ULP circuits, increase in will significantly reduce the drive current and hence the speed. Therefore, higher value of is not suitable for high performance ULP applications.
4. Effect of Doping Profile under Subthreshold Conditions
In scaled superthreshold transistors, halo and retrograde doping profiles are used to suppress short channel effects (SCE) like DIBL lowering and body punchthrough [20]. However, in subthreshold region, SCE plays a minor role as compared to superthreshold regime because of lower [11]. Hence, it has been established that halo and retrograde doping are less effective under subthreshold conditions. Also low doping level can reduce the bottom junction capacitance. Therefore, it is important to investigate the effect of doping profile under subthreshold conditions in nanometer technology domain.
It is observed from Figure 9 that the reductions in substrate () and halo doping increase the drain current () significantly. The decrease in doping concentration by 50% increases by 3.5x. Also reducing by 4x increases by 2.25x. However, from Figure 10, it is observed that reducing by 50% increases “” by 0.7 mV/decade and by 3.88x. Therefore, a trade-off is involved in improving the drive current, “,” and on reducing doping concentration. Similar performance trend is observed by changing the halo doping concentration. Figures 11 and 12 show the drive current and subthreshold slope as a function of halo and substrate doping.
5. Subthreshold Device Characterization
This section mainly targets improvement of the subthreshold slope so that energy consumption can be reduced [11]. The calibrated device is then tuned at optimum values of , , , and to achieve best subthreshold characteristics. Optimized device parameters from Section 4 are used to achieve better subthreshold slope under subthreshold conditions. Figure 13 shows the comparison of the subthreshold slope as a function of supply voltage for the conventional and the optimized device under subthreshold condition. As shown in Figure 13, the optimized device shows 9.89% improvement in subthreshold slope over the conventional device operated in subthreshold region. Also, as shown in Table 3, ratio increases by 34% in case of optimized device for the same drive current. Since effect of DIBL is very small under subthreshold conditions this work has not considered the DIBL during optimization.
6. Conclusion
The device designed for superthreshold circuits is not suitable for optimum subthreshold operation. This paper proposed new device process parameters to improve the subthreshold slope and to enhance the speed of subthreshold circuits. It has successfully concluded that optimizing the device for subthreshold region results in improvement in both the subthreshold slope and the ratio. Hence, in order to obtain the better performance of device under subthreshold conditions, it is necessary to optimize the process and geometry parameters of Si-MOSFET at nanometer technology node due to relaxed constraint for different leakage currents and short channel effects.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.