CMOS Image Sensor with On-Chip Image Compression:  A Review and Performance Analysis

<table>Block diagram of a typical system design integrated an image-sensor array and off-array processor, in which the 2D Haar wavelet image compression algorithm has been implemented as proposed in [<a href="/journals/js/2010/920693/#B52">56</a>].</table>

Journal of Sensors

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Figure 3: CMOS Image Sensor with On-Chip Image Compression:  A Review and Performance Analysis 