CMOS Image Sensor with On-Chip Image Compression:  A Review and Performance Analysis

<table>Architecture of high-speed CMOS image sensor with a resolution of <svg height="10.1125" id="M26" style="vertical-align:-0.28125pt" version="1.1" viewbox="0 0 57.349998 10.1125" width="57.349998" xmlns="http://www.w3.org/2000/svg">
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<tspan style="font-size: 11.21px; " x="11.208" y="0">6</tspan>
<tspan style="font-size: 11.21px; " x="19.300177" y="0">×</tspan>
<tspan style="font-size: 11.21px; " x="28.961472" y="0">2</tspan>
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</svg> integrated a DCT processor. Sample-hold function unit is implemented in pixel-level circuit for the global electronic shutters so as to enhance the speed of the overall system as proposed in [<a href="/journals/js/2010/920693/#B57">60</a>].</table>

Journal of Sensors

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Figure 6

Figure 6: CMOS Image Sensor with On-Chip Image Compression:  A Review and Performance Analysis 