| | Testing approach | Integrated digital devices | Analog mixed signal devices | Microelectromechanical systems |
| | Fault model | Assertion, gate delay, line delay, redundant, path delay, behavioral, branch, bus, cross-point, stuck-open, stuck-at, stuck-on, bridging, and so forth. | Hierarchical, behavioral, macro model, transistor, physical, catastrophic, and parametric faults and so forth. | Behavioral, shorts and opens in electrothermal and electromagnetic, structural defect level, parametric, functional, fatigue, and reliability model. |
| | Test technique | VHDL, HSPICE, fault dictionary, probabilistic, signature analysis method, LFSR (linear feedback shift register), BIST (built in self-test), and so forth. | Pole-Zero Analysis, artificial neural network, HSPICE, SABER, VHDL-AMS, ATPG, diagnosis of soft faults based on fractional correlation, BIST (built in self-test), and so forth. | Neural network, VHDL-AMS, device-level (FEM) and HDLs and transposition of techniques developed for microelectronics, BIST (built in self-test). |
|
|
