An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Abstract

Discrete Cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array) and SoC (system on chip). The linear-array DCT/IDCT processor with the computation complexity 𝑂(5𝑁/8) and hardware complexity 𝑂(5𝑁/8) is fully pipelined and scalable for variable-length DCT/IDCT computations.

1. Introduction

With rapid growth of modern communication applications and computer technologies, image compression and real-time computation of nonlinear time series continues to be in great demand. Discrete Cosine transform (DCT) is one of the major operations in various image/video compression standards [1] and nonlinear time series applications [2–8]. Though fast Fourier transform (FFT) can be used to implement DCT, it requires complex-valued computations; and moreover, N-point DCT by FFT contains 𝑂(log2𝑁+1) stages. The conventional DCT architectures using distributed arithmetic involve complex hardware with a great number of registers [9–19]. Other commonly used DCT architectures with matrix formulation and distributed memory [20–27] are however not suited for VLSI implementation because the hardware complex is proportional to the length of DCT, which leads to the scalability problem of variable-length DCT computations. In this paper, we propose the novel linear-array architecture for scalable DCT/IDCT implementation.

The remainder of this paper proceeds as follows. In Section 2, we propose the fast DCT/IDCT computation based on subband decomposition algorithm. In Section 3, the reconfigurable FPGA-based and programmable SoC implementations with low hardware cost are proposed for the fast DCT/IDCT computation. The performance comparison with conclusions can be found in Section 4.

2. Proposed Fast DCT/IDCT Computation

For an N-point signal, 𝑥[𝑛], the discrete cosine transform (DCT) [28] is defined as 𝐶[𝑘]=𝛼[𝑘]^𝑁−1_𝑛=0𝑥[𝑛]cos[(2𝑛+1)𝑘𝜋2𝑁], (2.1) where 𝑘=0,…,𝑁−1,𝛼[0]=1/√𝑁, and 𝛼[𝑘]=2/𝑁 for 𝑘>0. Let 𝑥_𝐿[𝑛] and 𝑥_𝐻[𝑛] denote the low-frequency and high-frequency subband signals of 𝑥[𝑛], respectively, which are defined as𝑥_𝐿1[𝑛]=2𝑥{𝑥[2𝑛]+𝑥[2𝑛+1]},_𝐻1[𝑛]=2{𝑥[2𝑛]−𝑥[2𝑛+1]}, (2.2) where 𝑛=0,1,2,…,(𝑁/2)−1. The original signal 𝑥[𝑛] can be obtained from 𝑥_𝐿[𝑛] and 𝑥_𝐻[𝑛] as follows: 𝑥[2𝑛]=𝑥_𝐿[𝑛]+𝑥_𝐻[𝑛],𝑥[2𝑛+1]=𝑥_𝐿[𝑛]−𝑥_𝐻[𝑛]. (2.3) As one can see, the DCT of 𝑥[𝑛] can be rewritten as𝐶[𝑘]=^(𝑁/2)−1_𝑛=0𝛼[𝑘]𝑥[2𝑛]cos((4𝑛+1)𝑘𝜋2𝑁)+^(𝑁/2)−1_𝑛=0𝛼[𝑘]𝑥[2𝑛+1]cos((4𝑛+3)𝑘𝜋)2𝑁=2cos(𝜋𝑘)2𝑁^(𝑁/2)−1_𝑛=0𝛼[𝑘]𝑥_𝐿[𝑛]cos((2𝑛+1)𝑘𝜋𝑁_{𝐶𝐿[𝑘]})+2sin(𝜋𝑘)2𝑁^(𝑁/2)−1_𝑛=0𝛼[𝑘]𝑥_𝐻[𝑛]sin((2𝑛+1)𝑘𝜋𝑁_{𝑆𝐻[𝑘]}), (2.4) where 𝐶_𝐿[𝑘] and 𝑆_𝐻[𝑘] are the subband DCT and DST (discrete sine transform) of 𝑥[𝑛], respectively.

2.1. Fast DCT Computation Based on Subband Decomposition Algorithm

Without loss of generality, the 8-point fast DCT based on subband decomposition algorithm is proposed for the widely used JPEG and MPEG-1/2 standards, which can be easily extended to variable-length DCT computations. The vector form of 8-point DCT can be written as𝐂₈=𝐓_{SB_DCT,8}𝐓_{SB_DST,88×8}⋅𝐱_𝐿𝐱_𝐻8×1, (2.5) where 𝐂₈=[𝐶[0]⋯𝐶[7]]^𝑇, 𝐱_𝐿=[𝑥_𝐿[0]⋯𝑥_𝐿[3]]^𝑇, 𝐱_𝐻=[𝑥_𝐻[0]⋯𝑥_𝐻[3]]^𝑇, and 𝐓_{𝑆𝐵_𝐷𝐶𝑇,8} and 𝐓_{𝑆𝐵_𝐷𝑆𝑇,8} denote the 8×4 matrices of subband DCT and subband DST, respectively, which can form orthonormal bases for the two orthogonal subspaces of 𝐑⁸. Notice that, due to the orthogonality between 𝐓_{𝑆𝐵_𝐷𝐶𝑇,8} and 𝐓_{𝑆𝐵_𝐷𝑆𝑇,8}, 𝑥_𝐿[𝑛] and 𝑥_𝐻[𝑛] can be obtained from 𝐶[𝑘] as follows: 𝑥_𝐿[𝑛]=^𝑁−1_𝑛=0𝛼[𝑘]cos(𝜋𝑘2𝑁)𝐶[𝑘]cos((2𝑛+1)𝑘𝜋𝑁𝑥),_𝐻[𝑛]=^𝑁−1_𝑛=0𝛼[𝑘]sin(𝜋𝑘2𝑁)𝐶[𝑘]sin((2𝑛+1)𝑘𝜋𝑁), (2.6) where 𝑛=0,1,2,…,𝑁/2−1, and 𝑁=8.

The proposed fast DCT algorithm is a subband decomposition-based multistage algorithm. Specifically, let 𝑥_𝐿𝐿1[𝑛]=2{𝑥_𝐿[2𝑛]+𝑥_𝐿𝑥[2𝑛+1]},_𝐿𝐻1[𝑛]=2{𝑥_𝐿[2𝑛]−𝑥_𝐿𝑥[2𝑛+1]},_𝐻𝐿1[𝑛]=2{𝑥_𝐻[2𝑛]+𝑥_𝐻𝑥[2𝑛+1]},_𝐻𝐻1[𝑛]=2{𝑥_𝐻[2𝑛]−𝑥_𝐻[2𝑛+1]}, (2.7) where 𝑛=0,1. And let𝑥_𝐿𝐿𝐿1[𝑛]=2{𝑥_𝐿𝐿[2𝑛]+𝑥_𝐿𝐿𝑥[2𝑛+1]},_𝐿𝐿𝐻1[𝑛]=2{𝑥_𝐿𝐿[2𝑛]−𝑥_𝐿𝐿𝑥[2𝑛+1]},_𝐿𝐻𝐿1[𝑛]=2{𝑥_𝐿𝐻[2𝑛]+𝑥_𝐿𝐻𝑥[2𝑛+1]},_𝐿𝐻𝐻1[𝑛]=2{𝑥_𝐿𝐻[2𝑛]−𝑥_𝐿𝐻𝑥[2𝑛+1]},_𝐻𝐿𝐿1[𝑛]=2{𝑥_𝐻𝐿[2𝑛]+𝑥_𝐻𝐿𝑥[2𝑛+1]},_𝐻𝐿𝐻1[𝑛]=2{𝑥_𝐻𝐿[2𝑛]−𝑥_𝐻𝐿𝑥[2𝑛+1]},_𝐻𝐻𝐿1[𝑛]=2{𝑥_𝐻𝐻[2𝑛]+𝑥_𝐻𝐻𝑥[2𝑛+1]},_𝐻𝐻𝐻1[𝑛]=2{𝑥_𝐻𝐻[2𝑛]−𝑥_𝐻𝐻[2𝑛+1]}, (2.8) where 𝑛=0. Based on subband decompositions using (2.2), (2.7), and (2.8), data flow of computing the 2-point subband DCT: 𝐂_𝐿𝐿,2 and subband DST: 𝐂_𝐿𝐻,2 for the 8-point DCT is shown in Figure 1. As one can see, data flow of computing 𝐂_𝐻𝐿,2 and 𝐂_𝐻𝐻,2 can be obtained in a similar way, and therefore is not shown in Figure 1. All of the 2-point subband DCTs and DSTs are given by𝐂_𝐿𝐿,2=𝐓_{SB_DCT,2}𝐓_{SB_DST,22×2}⋅𝐱_𝐿𝐿𝐿𝐱_{𝐿𝐿𝐻2×1}=𝐓_{SB_DCT,2}⋅𝐱_𝐿𝐿𝐿𝐶_{𝐿𝐿𝐿,2}+𝐓_{SB_DST,2}⋅𝐱_𝐿𝐿𝐻𝑆_{𝐿𝐿𝐻,2},𝐂_𝐿𝐻,2=𝐓_{SB_DCT,2}𝐓_{SB_DST,22×2}⋅𝐱_𝐿𝐻𝐿𝐱_{𝐿𝐻𝐻2×1}=𝐓_{SB_DCT,2}⋅𝐱_𝐿𝐻𝐿𝐶_{𝐿𝐻𝐿,2}+𝐓_{SB_DST,2}⋅𝐱_𝐿𝐻𝐻𝑆_{𝐿𝐻𝐻,2},𝐂_𝐻𝐿,2=𝐓_{SB_DCT,2}𝐓_{SB_DST,22×2}⋅𝐱_𝐻𝐿𝐿𝐱_{𝐻𝐿𝐻2×1}=𝐓_{SB_DCT,2}⋅𝐱_𝐻𝐿𝐿𝐶_{𝐻𝐿𝐿,2}+𝐓_{SB_DST,2}⋅𝐱_𝐻𝐿𝐻𝑆_{𝐻𝐿𝐻,2},𝐂_𝐻𝐻,2=𝐓_{SB_DCT,2}𝐓_{SB_DST,22×2}⋅𝐱_𝐻𝐻𝐿𝐱_{𝐻𝐻𝐻2×1}=𝐓_{SB_DCT,2}⋅𝐱_𝐻𝐻𝐿𝐶_{𝐻𝐻𝐿,2}+𝐓_{SB_DST,2}⋅𝐱_𝐻𝐻𝐻𝑆_{𝐻𝐻𝐻,2}. (2.9) Thus, we have 𝐂_𝐿𝐿,2𝐂_𝐿𝐻,2𝐂_𝐻𝐿,2𝐂_𝐻𝐻,2=𝐑₈⋅𝐱₈, (2.10) where 𝐱₈=[𝑥[0]⋯𝑥[7]]^𝑇 is the original signal, and𝐑₈=√28⋅111111111111−1−1−1−111−1−111−1−111−1−1−1−1111−11−11−11−11−11−1−11−111−1−111−1−111−1−11−111−1. (2.11)

Figure 1 

Data flow of computing the 2-point subband DCT: ${\mathbf{C}}_{LL,2}$ and subband DST: ${\mathbf{C}}_{LH,2}$ (for the 8-point DCT of the input signal: ${\mathbf{x}}_8$) based on subband decomposition.

Similarly, we have the following:𝐂_𝐿,4=𝐓_{SB_DCT,4}𝐓_{SB_DST,44×4}⋅𝐱_𝐿𝐿,2𝐱_{𝐿𝐻,24×1}=𝐓_{SB_DCT,4}⋅𝐱_𝐿𝐿,2𝐶_𝐿𝐿,4+𝐓_{SB_DST,4}⋅𝐱_𝐿𝐻,2𝑆_𝐿𝐻,4,𝐂_𝐻,4=𝐓_{SB_DCT,4}𝐓_{SB_DST,44×4}⋅𝐱_𝐻𝐿,2𝐱_{𝐻𝐻,24×1}=𝐓_{SB_DCT,4}⋅𝐱_𝐻𝐿,2𝐶_𝐻𝐿,4+𝐓_{SB_DST,4}⋅𝐱_𝐻𝐻,2𝑆_𝐻𝐻,4. (2.12) Figure 2 depicts the relationship between 𝐂_𝐿𝐿,4 and 𝐂_𝐿𝐿,2, which can be obtained by the following:𝐂_𝐿𝐿,4=𝐓_{𝑆𝐵_𝐷𝐶𝑇,4}⋅𝐱_𝐿𝐿,2,𝐂_𝐿𝐿,2=𝐓₂⋅𝑥_𝐿𝐿,2, (2.13)(2.14) According to (2.24)–(2.27), we have𝐅₈=2000000001.81230.750700.360500−0.14930001.847800.7654000−0.63641.536400.4252001.02660000002000.4252−1.026600.6364001.5364000−0.765401.8478000−0.3605−0.149301.812300−0.7507. (2.28) Finally, the proposed 8-point DCT computation based on subband decomposition is as follows:𝐂₈=𝐅₈⋅𝐑₈⋅𝐱₈, (2.29) where𝐅₈=2⋅1000000001000000000.92390.3827000000−0.38270.9239000000000.90620.37540.1802−0.07460000−0.1802−0.07460.9062−0.37540000−0.31820.76820.21260.513300000.2126−0.51330.31820.7682. (2.30) Figure 8 shows block diagram of the proposed DCT computation; one of the advantages is that 𝐑₈ is orthogonal, and all of the submatrices of 𝐅₈ are orthonormal.

Figure 4 

Data flow of computing ${\mathbf{C}}_{L,4}$ and ${\mathbf{C}}_{H,4}$ using 4-point subband DCT and DST.

Figure 5 

Data flow of computing ${\widehat{\mathbf{C}}}_{L,8}$ and ${\mathbf{C}}_{L,4}$ based on subband decomposition.

Figure 6 

Data flow of computing ${\widehat{\mathbf{S}}}_{H,8}$ and ${\mathbf{C}}_{H,4}$ based on subband decomposition.

Figure 7 

Data flow of computing ${\mathbf{C}}_8$ using 8-point subband DCT and DST.

Figure 8 

Block diagram of the proposed (8-point) fast DCT algorithm based on subband decomposition.

2.2. Fast IDCT Computation Based on Subband Decomposition Algorithm

According to (2.29), IDCT can be obtained by𝐱₈=𝐑₈⁻¹⋅𝐅₈⁻¹⋅𝐂₈, (2.31) where𝐑₈⁻¹=8√2,𝐅111111111111−1−1−1−111−1−111−1−111−1−1−1−1111−11−11−11−11−11−1−11−111−1−1111−1−11−1−11−111−1₈₋₁=12⋅.1000000001000000000.9239−0.38270000000.38270.9239000000000.9062−0.1802−0.31820.212600000.37540.37540.7682−0.513300000.18020.18020.21260.31820000−0.0746−0.07460.51330.7682 (2.32) As 𝐑₈ is orthogonal and all of the submatrices of 𝐅₈ are orthonormal, the inverse of 𝐑₈ and 𝐅₈ can be obtained easily. In addition, it takes only twenty multiplication operations for both DCT and IDCT.

3. VLSI Implementation of an Efficient Linear-Array DCT/IDCT Processor

Based on the proposed approach to fast DCT computation shown in Figure 8, an efficient architecture for implementing the fast DCT/IDCT processor is thus presented in this section. Recall that the DCT of a signal, 𝐱₈, can be efficiently obtained by 𝐂₈=𝐅₈⋅𝐑₈⋅𝐱₈. Let 𝐲₈=𝐑₈⋅𝐱₈, then we have 𝐂₈=𝐅₈⋅𝐲₈. Figure 9 shows the matrix-vector multiplication of 𝐑₈⋅𝐱₈, in which six CSA(3,2)s (carry-save-adder (3,2)) and one CSA (carry-save-adder) [29, 30] are utilized, and therefore four simple-addition time and one CSA computation time is required to compute each element of 𝐲₈. Figures 10 and 11 show the Multiplier array (MA) consisted of four multipliers and the CSA array (CA) consisted of eight CSAs, respectively, which are used to compute the matrix-vector computation of 𝐅₈⋅𝐲₈; thus, only one multiplication time with one CSA computation time is needed to compute each element of 𝐂₈, that is, the DCT coefficient. Table 3 depicts data flow of the proposed fast DCT processor with pipelined linear-array architecture [31]. As a result, only five multiplication cycles with five addition cycles are needed to compute 8-point DCT. In general, for N-point DCT, the computation time and hardware complexity of the proposed fast DCT processor are 𝑂(5𝑁/8) and 𝑂(𝑁/2), respectively.

Figure 9 

Fast adder (FA) for the matrix-vector multiplication of ${\mathit{R}}_8·{\mathit{x}}_8$. (Note: The width of buses is 32-bit.)

Figure 10 

Multiplier array (MA) consisted of four multipliers. (Note: The width of buses is 32-bit.)

Figure 11 

CSA array (CA) consisted of eight CSAs. (Note: The width of buses is 32-bit.)

Table 4 shows data flow of the proposed fast IDCT algorithm [31], where 𝐂₈ is the DCT of an 8-point signal 𝐱₈; 𝐳₈=𝐅₈⁻¹⋅𝐂₈, and 𝐱₈=𝐑₈⁻¹⋅𝐳₈. Figure 12 shows the so-called full CSA(4,2) (FCSA(4,2)) consisted of two CSA(3,2) and one CSA for the computation of 𝐳₈ [29, 30]. It is noted that the CSA array consisted of eight CSAs shown in Figure 11 can also be used for the computation of 𝐱₈. As shown in Table 4, only five multiplication cycles with three addition cycles are needed to compute 8-point IDCT. As one can see, the computation time and hardware complexity of the proposed fast IDCT architecture are the same as that of the proposed fast DCT architecture. In addition, only 16-word RAM/registers and 10-word ROM are required to store the intermediate results and constants, respectively; and the latency time is only 5-multiplication-cycle.

Figure 12 

Full CSA(4,2) consisted of two CSA(3,2) and one CSA.

Figure 13 shows system block diagram of the proposed fast DCT/IDCT architecture. The platform for architecture development and verification has been designed as well as implemented in order to evaluate the development cost. Figure 14 depicts block diagram of the platform, in which the 8051 microcontroller reads data from PC via DMA channel and writes the result back to PC by USB 2.0 bus; the Xilinx XC2V6000 FPGA chip implements the proposed DCT processor [32]. The architecture development and verification board shown in Figure 15 are to verify and evaluate the proposed DCT/IDCT architecture. Moreover, the reusable intellectual property (IP) DCT/IDCT core has also been implemented in Matlab for functional simulations. The hardware code written in Verilog is running on a workstation with the ModelSim simulation tool and Xilinx ISE smart compiler. In addition, the FPGA platform shown in Figure 14 is to verify and evaluate the proposed DCT architecture. It is noted that the throughput can be improved by using the proposed architecture while the computation accuracy is the same as that obtained by using the conventional one with the same word length.

Figure 13 

System block diagram of the proposed DCT/IDCT architecture (FA: fast-adder-array, MA: Multiplier array, FCSA(4,2): full CSA(4,2), and CA: CSA- array).

Figure 14 

Block diagram of the architecture development and verification platform for the proposed DCT/IDCT processor.

Figure 15 

The architecture development and verification board.

The SoC is synthesized by the TSMC 0.18 𝜇m 1P6M CMOS cell libraries [33]. The physical circuit is synthesized by the Astro tool. The circuit is evaluated by DRC, LVS, and PVS [34]. Figure 16 shows the cell-based design flow. The layout view of the 8-point DCT/IDCT processor with 32-bit operand is shown in Figure 17. The core areas are obtained by the Synopsys design analyzer. The power consumptions are obtained by the PrimePower. The reported core size of the implemented the proposed processor is 1520×1520𝜇m² and the power dissipation is 102.2 mW at 1.8 V with clock rate of 1 GHz. Thus, the proposed programmable DCT/IDCT architecture is able to improve the power consumption and computation speed significantly. All the control signals are internally generated on-chip. The proposed DCT/IDCT processor provides both high-throughput and low gate count.

Figure 16 

Cell-based design flow.

Figure 17 

The layout view of the proposed 8-point DCT/IDCT processor with 32-bit operand.

The proposed reconfigurable DCT/IDCT processor used to compute 8/16/32/64-point DCT/IDCT on FPGA are composed mainly of the 8-point DCT/IDCT core; the computation complexity using a single 8-point DCT/IDCT core is O(5N/8) for extending N-point DCT/IDCT computation. Note that the transform matrices used for the proposed linear array with 8-point DCT core can be extended to a variety of different sizes. Thus, the proposed architecture is highly scalable.

The linear-array architecture with use of hardware resources has been proposed for trade offs of performance, chip area and power consumption. As a result, it has the advantage of balancing the need for power saving with computation speed.

4. Conclusion

By taking advantage of subband decomposition, a high-efficiency architecture with pipelined structures is proposed for fast DCT/IDCT computation. Specifically, the proposed DCT/IDCT architecture not only improves throughput by more than two times that of the conventional architectures [9–11, 15–19], but also saves memory space significantly [1, 9–22]. Table 1 shows comparisons between the proposed architecture and the conventional architectures [1, 9–14] (with dual memory banks), and [15–19]. Table 2 shows comparisons with other commonly used architectures [1, 12–14, 20–24]. For 8×8 DCT, the algorithm proposed by Feig requires 54 multiplications and 462 additions [27]; the proposed method requires 25 multiplications and 100 additions. Thus, the performance of this work is superior to that of the Feig algorithm. In addition, the proposed fast DCT/IDCT architecture is highly regular, scalable, and flexible. The DCT/IDCT processor designed by using the portable and reusable Verilog is a reusable IP, which can be implemented in various processes; combined with efficient use of hardware resources for tradeoffs of performance, area and power consumption; and therefore is much suited to the JPEG and MPEG-1/2 applications.

Table 1 

Comparisons between the proposed architecture and the conventional architectures.

Table 2 

Comparisons of the proposed architecture and other commonly used architectures.

Table 3 

Data flow of the proposed fast DCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).

Table 4 

Data flow of the proposed fast IDCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).

Acknowledgments

The National Science Council of Taiwan, Taipei, Taiwan, under Grant NSC98-2221-E-216-037 and the Chung Hua University, Hsinchu, Taiwan, under Grant no. CHU-NSC98-2221-E-216-037 supported this work.