An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Table 2

Comparisons of the proposed architecture and other commonly used architectures.

8-point	Lee et al. [20]	Chang and Wang [21]	Hsiao and Shiue [22]	Hsiao and Tseng [23]	Hou [24]	Sung [1, 9–14]	This work
DCT/IDCT	DCT/IDCT	DCT/IDCT	DCT	DCT/IDCT	DCT/IDCT	DCT/IDCT	DCT/IDCT
Real multipliers	28	64	—	—	—	—	4
CORDIC processors	—	—	—	—	3	5	—
Real adders	134	88	9	10	14	18	26
Complex multipliers	—	—	3	3		—	—
Delay elements (Words)	256	114	—	171	—	—	—
Memory (Words)	$~$384	$~$200	$~$370	—	—	70	26
Hardware complexity	$O(N\log \hspace{0.17em}N)$	$O(N^2)$	$O(\log \hspace{0.17em}N)$	$O(\log \hspace{0.17em}N)$	$O(\log \hspace{0.17em}N)$	$O(N-\log \hspace{0.17em}N)$	$O(N/2)$
Computation complexity	$O(\log \hspace{0.17em}N)$	$O(N)$	$O(N\log \hspace{0.17em}N)$	$O(N\log \hspace{0.17em}N)$	$O(N\log \hspace{0.17em}N)$	$O(N)$	$O(5N/8)$
Pipelinability	no	no	no	no	yes	yes	yes
Scalability	poor	poor	good	good	good	good	better