An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Table 4

Data flow of the proposed fast IDCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).

Processor	MA	FCSA(4,2)	CA
Mul.-cycle_1	$C[2]·0.9239\text{,}$$C[3]·(-0.3827)$; $C[2]·0.3827\text{,}$$C[3]·0.92393$	$z[0]\text{,}$$z[1]$	—
Mul.-cycle_2	$C[4]·0.9062\text{,}$$C[5]·(-0.1802)\text{,}$$C[6]·(-0.3182)\text{,}$$C[7]·0.2126$	$z[2]\text{,}$$z[3]$	$\text{C}\_0+\text{C}\_1=\text{C}\_01$
Mul.-cycle_3	$C[4]·0.3754\text{,}$$C[5]·0.3754\text{,}$$C[6]·0.7682\text{,}$$C[7]·(-0.5133)$	$z[4]$	$\text{C}\_01+\text{C}\_2=\text{C}\_02$
Mul.-cycle_4	$C[4]·(-0.3182)\text{,}$$C[5]·0.7682\text{,}$$C[6]·0.2126\text{,}$$C[7]·0.5144$	$z[5]$	$\text{C}\_02+\text{C}\_3=\text{C}\_03$
Mul.-cycle_5	$C[4]·0.2126\text{,}$$C[5]·(-0.5133)\text{,}$; $C[6]·0.3182\text{,}$$C[7]·0.7682$	$z[6]$	$\text{C}\_03+\text{C}\_4=\text{C}\_04$
Add.-cycle_1	—	$z[7]$	$\text{C}\_04+\text{C}\_5=\text{C}\_05$
Add.-cycle_2	—	—	$\text{C}\_05+\text{C}\_6=\text{C}\_06$
Add.-cycle_3	—	—	$\text{C}\_06+\text{C}\_7=\text{C}\_07$; $x[0]\text{,}$$x[1]\text{,}$$x[2]\text{,}$$x[3]\text{,}$; $x[4]\text{,}$$x[5]\text{,}$$x[6]\text{,}$$x[7]$