Quantization Effects on Period Doubling Route to Chaos in a ZAD-Controlled Buck Converter

Abstract

The quantization effect in transitions to chaos and periodic orbits is analyzed in this paper through a specific application, the zero-average-dynamics- (ZAD-) controlled buck power converter. Several papers have studied the quantization effects in the one periodic orbit and some authors have given guidelines to design digitally controlled power converter avoiding limit cycles. On the other hand many studies have been devoted to analyze the ZAD-controlled buck power converter, but these past studies did not include hardware considerations. In this paper, analog-to-digital conversion process is explicitly introduced in the modeling stage. As the feedback gain is varied, the dynamic behavior depending on the analog-to-digital converter resolution is numerically analyzed. Particularly, it is observed that including the quantizer in the model carries out several changes in the transitions to chaos, which include interruption of band-merging process by cascades of periodic inclusions, disappearing of band transitions, and multiple coexisting of periodic orbits. Many of these phenomena have not been reported as a consequence of the quantization effects.

1. Introduction

In the recent years, many physical systems have been modelled using the theory of nonsmooth dynamical systems (NSDSs) [1]. The piecewise smooth dynamical system (PWS) approach has mainly been used to model nonsmooth phenomena such as switching, saturation, sliding, or impacting events [2, 3]. A good compromise between simplicity and accuracy has been achieved using PWS models in many works [4, 5]. However, some applications could require additional considerations to achieve equivalence between the mathematical model and real system responses, as we report in this paper.

Nonsmooth systems controlled by digital techniques can require more elaborate models depending on hardware specifications or the sensitivity of the systems. Analog-to-digital conversion (ADC) processes can modify the dynamic behavior of the system due to phenomena such as quantization level or conversion time.

Power converters are modelled as PWS due to the switching action of transistors and diodes and saturation action in the PWM controller (see, e.g., [6]). Bifurcations and chaos have been detected in many power electronic models. For a broad study of nonlinear phenomena exhibited by power converters, see [7]. On the other hand, in the last decade the ZAD strategy has been developed for controlling DC-DC buck power converters. This controller forces a defined function to have zero average for each sampling period. In this case, the function 𝑠_{𝑝𝑤𝑚𝑙}(𝑡) is defined as a linear combination of the values of the error and its derivative at the switching instants (i.e., 𝑠_{𝑝𝑤𝑚𝑙}(𝑡)∶=𝑓(𝑒(𝑘𝑇),𝑒(̇𝑘𝑇)). Previous theoretical and numerical studies have demonstrated that the ZAD strategy offers two important advantages: very low error [8] and fixed switching frequency [9, 10]. In [10] a complete study for an ideal model of the ZAD-controlled converter was presented, when the parameter 𝐾_𝑠 varies.

In this paper, a new model for the ZAD-controlled buck power converter is introduced and the ADC process is included explicitly for acquisition of the state variables values, that is, current flowing to the inductor and voltage across the capacitor. Data acquisition by the sensors and signal digitizing by the A/D converters are two crucial processes in the performance of the ZAD controller; however, in this paper only the dynamic behavior depending on the resolution of the A/D converters is analyzed. This resolution affects the accuracy of the state variable values changing the performance of the ZAD controller. Although some authors have included digitalization effects of analog-to-digital (A/D) and digital-to-analog (D/A) converters in different systems, either linear [11, 12] or nonlinear (such as power converters) [13, 14], their main conclusions are that the ADC processes can generate limit cycles in the dynamic behavior of the systems.

The paper is organized as follows: Section 2 presents the mathematical framework to analyze and control the buck converter. Section 3 presents a detailed analysis of the quantization effects in the transition to chaos for a ZAD-controlled buck converter, introducing the model of the ADC process and changing its resolution 𝑛 (𝑛∈{8,12,16}). In Section 4, conclusions are presented.

2. Mathematical Model and Physical Considerations

2.1. Buck Converter

A complete study of the applications and design of power converters can be found in [15, 16]. A simplified diagram of the closed-loop synchronous buck converter is shown in Figure 1(a). Its main feature is that the output value 𝑉_𝑜 is lower than the source 𝑉_in (step-down converter). The switches 𝑆₁ and 𝑆₂ operate in a complementary way; that is, when 𝑆₁ is on, the switch 𝑆₂ is off and vice versa.

(a) ZAD-controlled buck converter

(b) Analog-to-digital conversion process

Figure 1 

Schematic diagram for digitally controlled buck power converter and digital conversion process.

The mathematical model for the synchronous buck converter can be expressed in a compact form as: 𝑥̇₁𝑥̇₂=−11𝑅𝐶𝐶−1𝐿0𝑥₁𝑥₂+0𝑉_in𝐿𝑢, (2.1) where 𝑥₁=𝑣_𝐶, 𝑥₂=𝑖_𝐿, and 𝑢 belongs to discrete set {0,1}. The objective of controlling the buck converter is related to regulation or tracking tasks. In this paper the converter is used as a regulator. The next step is to design a control strategy so that the load voltage is regulated to a desired value. the duty cycle 𝑑, which is defined as the ratio between the time that the switch 𝑆₁ is on (𝑢=1) and the sampling time 𝑇 in each 𝑇 (𝑇=50𝜇s in this work). In particular the duty cycle is computed as 𝑑=sat(𝐷_𝑘/𝑇), and 𝐷_𝑘 is computed according to ZAD control technique as it is explained in Section 2.2. After the duty cycle is computed, the control sequence to be applied to (2.1) during one sampling time is given by 𝑢=1if𝑘𝑇≤𝑘𝑇+𝑑𝑇2,0if𝑘𝑇+𝑑𝑇2<𝑡<(𝑘+1)𝑇−𝑑𝑇2,1if(𝑘+1)𝑇−𝑑𝑇2≤𝑡≤(𝑘+1)𝑇. (2.2)

2.2. ZAD Strategy

The control strategy is based on the concept of zero-average dynamics on the function 𝑠_𝑝𝑤𝑙 [9, 17, 18]. The ZAD strategy can be summarized as follows: (1) to choose dynamics that will be forced to have a zero average, (2) to force the dynamics to have zero average in each sampling period, and (3) to compute the duty cycle. As reported in [9, 19, 20], one of the possibilities for choosing the output dynamics is to define it as a piecewise-linear function given by 𝑠_𝑝𝑤𝑙(𝑡)=𝑠₁+(𝑡−𝑘𝑇)𝑠₁̇if𝑘𝑇≤𝑡≤𝑡₁,𝑠₂+𝑡−𝑡₁𝑠₂̇if𝑡₁<𝑡<𝑡₂,𝑠₃+𝑡−𝑡₂𝑠₁̇if𝑡₂≤𝑡≤(𝑘+1)𝑇. (2.3) Taking into account (2.2) where 𝑢=1 in the first part of the interval, after 𝑢=0 to finally return to 𝑢=1, then each part of 𝑠_𝑝𝑤𝑙(𝑡) is defined as 𝑠₁=𝑥₁−ref+𝐾_𝑠𝑥̇₁(𝐿𝐶)_{𝑥=𝑥(𝑘𝑇),𝑢=1},𝑠₂=𝐷_𝑘2𝑠₁̇+𝑠₁,𝑠₃=𝑠₂+𝑇−𝐷_𝑘𝑠₂̇,𝑠₁̇=𝑥̇₁+𝐾_𝑠(𝐿𝐶)𝑥̈_{1𝑥=𝑥(𝑘𝑇),𝑢=1},𝑠₂̇=𝑥̇₁+𝐾_𝑠(𝐿𝐶)𝑥̈_{1𝑥=𝑥(𝑘𝑇),𝑢=0},𝑡₁𝐷=𝑘𝑇+^𝑘2,𝑡₂𝐷=𝑘𝑇+𝑇−^𝑘2. (2.4)𝐾_𝑠 is a dimensionless positive constant and 𝑘∈0,1,2…. Therefore, the zero average condition is ^(𝑘+1)𝑇_𝑘𝑇𝑠_𝑝𝑤𝑙(𝑡)𝑑𝑡=0. (2.5) To find 𝐷_𝑘, (2.5) is solved to obtain 𝐷_𝑘=2𝑠₁+𝑇𝑠₂̇𝑠₂̇−𝑠₁̇. (2.6)

Finally, due to saturation effects, it is necessary to limit the duty cycle based on the sampling time. The duty cycle to be applied to the system is defined as 𝐷𝑑=1if^𝑘𝑇𝐷>1,_𝑘𝑇𝐷if0≤^𝑘𝑇𝐷≤1,0if^𝑘𝑇<0. (2.7)

2.3. Analog-to-Digital Conversion Process

As the ZAD strategy will be implemented in a digital platform, the ADC process must be included in the modelling stage. The main parts of the ADC process are sample and hold, and quantization and encoder processes [21].

2.3.1. Sample and Hold

The sample and hold process consists of catching the value of the signal to be sampled at a given instant 𝑘𝑇 (sampling) and holding it until the instant 𝑘𝑇+𝑇. Then the value of the signal 𝑥(𝑡)∶=𝑥(𝑘𝑇)∀𝑡∈[𝑘𝑇,𝑘𝑇+𝑇).

2.3.2. Quantization Process

The quantization process consists of transforming a continuous signal into a finite set of values. The quantization refers to an operation characterized by the relationship between the output signal, that is, one element of the finite discrete set, and the input signal, a continuous value. In Figure 1(b), the dashed line represents the input, and the staircase functions are the output. ℎ is the quantization level, that is, the value of the least significant bit (LSB) of the quantization process, and it can be expressed mathematically as 𝑉ℎ=^refℎ𝑖2^𝑛, (2.8) where 𝑛 is the number of bits of the analog-to-digital converter and 𝑉_refℎ𝑖=5V is the upper reference voltage.

3. Bifurcation Analysis

In this section, the dynamic behavior of a DC-DC buck power converter controlled by the ZAD strategy is analyzed, when the ADC process is included in the modeling stage.

The transition from periodicity to chaos in the system without the ADC process was studied in [9, 10]. Although in those papers the signal control 𝑢∈{−1,1}, the bifurcation diagrams do not show important changes when 𝑢∈{0,1}. The dynamic behavior of the system with 8-, 12- or 16-bit ADC resolution has significant differences from the system without an ADC process.

In this section, bifurcation diagrams of the model for different resolutions of the A/D converter are shown. Later, the observed dynamics are compared and discussion about the quantization effects is presented. In this particular case 𝑅=20Ω, 𝐶=40𝜇F, 𝐿=2mH, and 𝑉_in=40V. The desired output voltage is ref=32V. All bifurcation diagrams are made considering the samples of the states every 𝑇 seconds, that is, based on the stroboscopic map.

The system without ADC process (or with an ideal ADC process) has an asymptotically stable 1𝑇-periodic orbit for values of 𝐾_𝑠 larger than 3.25. Bifurcation diagrams of a buck converter controlled with the ZAD strategy and neglecting the ADC process are presented in Figure 2. The first bifurcation occurs near 𝐾_𝑠=3.25, and it is a flip type. As 𝐾_𝑠 is reduced, the system undergoes successive smooth and nonsmooth bifurcations. Period-doubling and border-collision bifurcations generate 2𝑇-, 4𝑇-, and 8𝑇-periodic orbits and chaotic bands with different numbers of saturated cycles, depending on nonsmooth transitions. A rigorous continuation method was applied in [19] to determinate ranges of stability and existence for the 1𝑇-, 2𝑇-, and 4𝑇-periodic orbits. The successive smooth and nonsmooth bifurcations in a very narrow range of 𝐾_𝑠 close to 3 cause the transition from periodic orbits to chaotic bands. Band-merging processes due to crisis bifurcations are observed for 𝐾_𝑠∈[0.1,3). The transition between one-band chaos and two-band chaos occurs near 𝐾_𝑠≈0.4, the transition between two-band chaos and four-band chaos is close to 𝐾_𝑠≈0.75, and the transition between four-band chaos and eight-band chaos is close to 𝐾_𝑠≈1.2. The period-doubling band process continues until the 𝐾_𝑠 value is close to 3.

(a) Voltage error diagram

(b) Current error diagram

(c) Duty cycle diagram

Figure 2 

Bifurcation diagrams of the system without ADC process (or with an ideal ADC process).

The inclusion of the ADC process affects the dynamic behavior of the system. Technical specifications of the A/D converters, mainly their resolution, change the behavior of the ZAD-controlled buck converter. Other aspects such as resolution of the digital PWM, noise, or precision of arithmetic calculations in the digital platform also have effects on the transition to chaos. In this paper it is considered that digital PWM has infinity resolution.

Figure 3 shows bifurcation diagrams of the model with the ADC process when 𝐾_𝑠 is varied.

(a)  8 bits

(b) 12 bits

(c) 16 bits

(d) 8 bits

(e) 12 bits

(f) 16 bits

(g) 8 bits

(h) 12 bits

(i) 16 bits

Figure 3 

Bifurcation diagrams varying 𝐾𝑠 and the ADC resolution. ((a)–(c)) Voltage error diagrams (𝑒1) for 8, 12 and 16 bits, respectively. ((d)–(f)) Current error diagrams (𝑒2) for 8, 12, and 16 bits, respectively. ((g)–(i)) Duty cycle diagrams for 8, 12, and 16 bits, respectively.

Three ADC resolutions are considered: 8, 12, and 16 bits. The remaining parameters are the same in all cases. To compare regulation errors, voltage error (𝑒₁(𝑘𝑇)) and current error (𝑒₂(𝑘𝑇)) are depicted instead of capacitor voltage (𝑉_𝐶(𝑘𝑇)) and inductor current (𝐼_𝐿(𝑘𝑇)). The variables 𝑒₁(𝑘𝑇) and 𝑒₂(𝑘𝑇) are defined as follows: 𝑒₁()=𝑉𝑘𝑇100_𝐶(𝑘𝑇)−ref,𝑒ref₂()=𝐼𝑘𝑇100_𝐿(𝑘𝑇)−ref₂ref₂ (3.1) with ref₂=ref/𝑅. The quantization effects in the dynamical behavior of the system can be divided into two analyses. (i)Quantization effects in chaos and band chaos dynamics. In this case, the parameter 𝐾_𝑠 is bounded to the range (0.1,3), and the ADC resolution belongs to the set {8,12,16}.(ii)Quantization effects in periodic dynamics. In this case, the parameter 𝐾_𝑠 is bounded to the range (3,7), and the ADC resolution belongs to the set {8,12,16}.

Next, the main effects of A/D converters on aperiodic and periodic dynamics are analyzed. Interesting phenomena can be seen.

3.1. Quantization Effects in Chaos and Band Chaos Dynamics

The system without an A/D converter has a period-doubling band bifurcation scenario in the range between 𝐾_𝑠=0.1 and 𝐾_𝑠=3 (see Figure 2). The structure of the chaos and band chaos dynamics is affected by the A/D converter resolution. Drastic variations in the dynamic behavior can be observed when the A/D converter resolution is fixed to 𝑛=8bits. The band-merging process is interrupted by cascades of periodic inclusions. Only the transition between one-band chaos and two-band chaos is preserved near 𝐾_𝑠≈0.4. Other band transitions disappear. The presence of chaos and band chaos dynamics drastically diminishes, and the sensitivity to initial conditions and coexistence of periodic solutions increase considerably. The system converges to different basins of attraction depending on the initial conditions. Dynamics with 8-bit A/D converters move to the right in the axis 𝑉_𝐶 and remain in the same range in the axis 𝐼_𝐿. Therefore, voltage error at the sampling time (𝑒₁(𝑘𝑇)) increases approximately from 0.2% to 0.3%, while current error (𝑒₂(𝑘𝑇)) remains in the range between −10% and 10% (see Figures 3(a) and 3(d)).

Figures 3(b), 3(e), and 3(h) show bifurcation diagrams of the system for 12-bit ADC resolution. Overlapping cascades of periodic orbits interspersed with chaos and band chaos attractors are observed. Two band transitions are preserved: one-band chaos to two-band chaos near 𝐾_𝑠≈0.4 and two-band chaos to four-band chaos near 𝐾_𝑠≈0.75. The presence of chaos and band chaos increases.

An interesting phenomenon associated with the two crisis bifurcations was detected. The bifurcation diagrams (Figures 3(b), 3(e), and 3(h)) show an abrupt change of dynamic behavior between the two crisis bifurcations in the interval 𝐾_𝑠∈(0.54,0.61). Different periodic windows can be seen depending on the initial conditions. Chaotic transients and fractal basin boundaries are also present. These phenomena have been studied in several works [22–24]. The appearance of transient chaos is relevant to the evolution of the saddle sets [25]. A chaotic saddle, also known as a nonattracting chaotic set, usually leads to chaotic transients and fractal basin boundaries [26]. In our case, the collision between the chaotic attractor and the unstable periodic orbit when the crisis occurs for 𝐾_𝑠≈0.4 induces the formation of transient chaos and fractal basins of attraction. Figure 4 shows transient responses for 𝐾_𝑠=0.55 with different initial conditions. Small variations in 𝑉_𝐶0 demonstrate the extreme sensitivity to the initial conditions of the system.

(a)   𝑉𝐶0=24.297—Chaos

(b) 𝑉𝐶0=24.298—4 per. with transient chaos

(c) 𝑉𝐶0=24.301—24𝑇-periodic orbit

Figure 4 

Transient responses of the system for 12-bit ADC resolution and different voltage initial conditions 𝑉𝐶0. The ZAD parameter is 𝐾𝑠=0.55 and the current initial condition (𝐼𝐿0) is 1.8.

However, very high periodic orbits (of order 100 or 1000) could be mistaken for chaos attractors. Some attractors have a chaotic shape, but the state variables are located with a bounded dispersion. This finding suggests the existence of a sequence with a very long periodic pattern. Figure 5 was generated to illustrate this phenomenon. State variables generated by nonsaturated duty cycles are shown in blue. State variables generated by saturated duty cycles to 𝑑_𝑘=0% are shown in green, and state variables generated by saturated duty cycles to 𝑑_𝑘=100% are shown in red.

(a)   𝐾𝑠=0.125—without ADC

(b) 𝐾𝑠=0.5—without ADC

(c) 𝐾𝑠=1—without ADC

(d) 𝐾𝑠=0.125—16 bits

(e) 𝐾𝑠=0.5—16 bits

(f) 𝐾𝑠=1—16 bits

(g) 𝐾𝑠=0.125—12 bits

(h) 𝐾𝑠=0.5—12 bits

(i) 𝐾𝑠=1—12 bits

(j) 𝐾𝑠=0.125—8 bits

(k) 𝐾𝑠=0.5—8 bits

(l) 𝐾𝑠=1—8 bits

Figure 5 

𝑉𝐶 versus 𝐼𝐿 phase portraits varying 𝐾𝑠 and the ADC resolution. ((a), (d), (g), (j)) 𝐾𝑠=0.125 without and with 16-, 12-, and 8-bit ADC, respectively. ((b), (e), (h), (k)) 𝐾𝑠=0.5 without and with 16-, 12-, and 8-bit ADC, respectively. ((c), (f), (i), (l)) 𝐾𝑠=0.125 without and with, 16-, 12-, and 8-bit ADC, respectively.

Figures 5(a), 5(b), and 5(c) show the chaotic dynamics for the system with an ideal ADC process. A one-band chaos attractor for 𝐾_𝑠=0.125, two-band chaos attractor for 𝐾_𝑠=0.5, and four-band chaos attractor for 𝐾_𝑠=1 are presented. Any periodic pattern can be defined because the state variables are always located at different points.

The presence of chaotic dynamics diminishes as ADC resolution decreases. The system does not have chaotic attractors for any value of 𝐾_𝑠∈{0.125,0.5,1} if the AD converter has 8-bit resolution. Different periodic orbits are observed: an 8𝑇-periodic orbit with seven nonsaturated cycles and one saturated cycle to 𝑑_𝑘=100% for 𝐾_𝑠=0.5 (Figure 5(k)) and an 18𝑇-periodic orbit with 14 nonsaturated cycles and 4 saturated cycles to 𝑑_𝑘=100% for 𝐾_𝑠=1 (Figure 5(l)). The attractor for 𝐾_𝑠=0.125 has a chaotic shape, but the state variables are located in a finite set of values. The size of this set is near 200; therefore, the periodicity of this attractor is near 200 (Figure 5(j)).

The same situation occurs with the attractors generated with 12-bit ADC resolution. Attractors generated with 𝐾_𝑠 in the set {0.125,0.5,1} have chaotic shapes, but the state variables are located in sets of finite size. The size of these sets is of the order of 1000. See Figures 5(g), 5(h), and 5(i).

Figures 3(c), 3(f), and 3(i) show the bifurcation diagrams of the system for 16-bit ADC resolution. These bifurcation diagrams are very close to the responses for an ideal ADC process. The band-merging process is observed without significant changes. Three band transitions are distinguished: one-band to two-band near 𝐾_𝑠≈0.4, two-band to four-band transition near 𝐾_𝑠≈0.75, and four-band to eight-band transition near 𝐾_𝑠≈1.2. The presence of chaos and band chaos dynamics is more clear. Attractors generated with 𝐾_𝑠 in the set {0.125,0.5,1} have chaotic shapes and the dispersion of state variables is very close to the ideal case. All numerical proofs indicate that the responses shown in Figures 5(d), 5(e), and 5(f) are chaos and band chaos dynamics. In these cases, the possibility of extremely high periodic patterns is not considered because the dispersion of the state variables cannot be limited to a finite set.

Although the dynamic properties show important variations when ADC resolution is varied, the statistical properties are not significantly modified. Table 1 shows the evolution of the mean value and standard deviations when the ADC resolution is varied between 2 bits and 16 bits for 𝐾_𝑠=0.125. Differences between chaotic dynamics and very high periodic orbits are not detected by these statistical measures. However, the results of this table confirm that 8- or fewer-bit A/D converter resolution affects the regulation condition of the system. Table 2 summarizes the same test for 𝐾_𝑠=1, when the ideal model has four-band chaos. These results are very close when the ADC resolution is 10, 12, 14, or 16.

Table 1 

Variation of the mean values and standard deviations of the state variables when the ADC resolution is varied and 𝐾_𝑠=0.125.

Table 2 

Variation of the mean values and standard deviations of the state variables when the ADC resolution is varied and 𝐾_𝑠=1.

3.2. Quantization Effects in Periodic Dynamics

The system without an A/D converter has a 1𝑇-periodic orbit for 𝐾_𝑠∈(𝐾_𝑐,7). At 𝐾_𝑠=𝐾_𝑐≈3.25, the system experiences a flip bifurcation, and a stable 2𝑇-periodic orbit exists for 𝐾_𝑠∈(3,𝐾_𝑐). Significant changes in the dynamical behavior can be observed for 8-bit ADC resolution; periodic and quasiperiodic orbits are induced in the range 𝐾_𝑠∈(3,7).

Quasiperiodic and periodic dynamics coexist when the resolution of the ADC converter is fixed to 8 bits and the range of 𝐾_𝑠∈(3,6), while coexisting periodic solutions are detected when 𝐾_𝑠>6. Figure 6(d) shows an example of a quasiperiodic dynamic of the system for an 8-bit ADC process and 𝐾_𝑠=5.2. Low-frequency oscillation is induced by the ADC process. Figure 6(a) shows an example of a 2𝑇-periodic orbit when 𝐾_𝑠=6.5. Other periodic dynamics are also possible depending on the initial conditions. Coexistence phenomena will be analyzed shortly.

(a)   𝐾𝑠=6.5 with 8 bits

(b) 𝐾𝑠=5.9 with 12 bits

(c) 𝐾𝑠=3.15 with 16 bits

(d) 𝐾𝑠=5.2 with 8 bits

(e) 𝐾𝑠=5.84 with 12 bits

(f) 𝐾𝑠=3.28 with 16 bits

Figure 6 

Examples of periodic and quasi periodic orbits for the system with 8-, 12-, and 16-bit ADC, respectively.

Periodic and quasiperiodic orbits can be identified for 12-bit ADC resolution depending on 𝐾_𝑠 and the initial conditions. Periodic behavior can be interrupted by quasiperiodic windows and extreme sensitivity to initial conditions can be distinguished. Figures 6(b) and 6(e) show examples of periodic and quasiperiodic orbits in the system with a 12-bit ADC process.

Dynamic behavior for 16-bit ADC resolution is very close to the behavior with an ideal ADC process. Quasiperiodic behavior can be detected near the flip transition for 𝐾_𝑠≈3.25. The induced oscillation has lower frequency than the cases with 8 and 12 bits. See Figure 6(f).

Statistical measures show that the dynamic behavior tends toward the response of the ideal ADC process when ADC resolution is increased. Table 3 summarizes the mean values and standard deviations of state variables when ADC resolution is varied from 𝑛=2 to 𝑛=16 and 𝐾_𝑠=4.5.

Table 3 

Variation of the mean values and standard deviations of the state variables when the ADC resolution is varied and 𝐾_𝑠=4.5.

Coexistence of dynamics is the most interesting and representative phenomenon detected in these bifurcation scenarios. A particular case when the ZAD parameter is fixed to 𝐾_𝑠=6.5 and ADC resolution is selected from the set {8,12,16} is presented in the following.

Three common characteristics were identified in the three cases: (i)multiple coexisting periodic solutions depending on the initial conditions, (ii)fractal basin boundaries characterized by extreme sensitivity to the initial values, (iii) duty cycle sequences of coexisting periodic solutions are composed by nonsaturated values; that is, 0%<𝑑<100%. Additionally, some nonsaturated duty cycles can be the same for two or more coexisting solutions. Small changes in a duty cycle value or in a recurrence pattern produce different periodic solutions.

Table 4 summarizes the characteristics of sixteen periodic orbits for 𝐾_𝑠=6.5 and 8-bit ADC resolution. Also, 1𝑇-, 2𝑇-, 3𝑇-, 6𝑇-, 10𝑇-, 11𝑇-, and 22𝑇-periodic orbits are possible depending on the initial conditions of the voltage capacitor 𝑉_𝐶0 and inductor current 𝐼_𝐿0. Figure 7 shows the evolution of several cases presented in Table 4. For 𝑉_𝐶0=0.4 and 𝐼_𝐿0=1 there is a stable 1𝑇-periodic orbit. The 1𝑇-periodic orbit is characterized by a duty cycle of 79.53%, reaching low stationary error and fixed-frequency condition.

Table 4 

Examples of coexisting periodic orbits for 8-bit ADC resolution and 𝐾_𝑠=6.5. 𝐼_𝐿0=1.5.

(a)   Case 1—1 per

(b) Case 2—2 per

(c) Case 4—2 per

(d) Case 7—2 per

(e) Case 9—3 per

(f) Case 10—6 per

(g) Case 11—6 per

(h) Case 12—6 per

(i) Case 13—10 per

(j) Case 14—10 per

(k) Case 15—11 per

(l) Case 16—22 per

Figure 7 

Examples of coexisting periodic orbits for 8-bit ADC resolution and 𝐾𝑠=6.5. More analysis is presented in Table 4.

Seven possibilities for 2𝑇-periodic orbits are detected. All of them are defined by two nonsaturated cycles (𝑑₁ and 𝑑₂). The 3𝑇-periodic dynamics can be obtained with a duty cycle sequence (𝑑₁,𝑑₂,𝑑₃) where 𝑑₁=𝑑₂=79.89% and 𝑑₃=81.58%. Figure 7(g) shows the evolution of the 3𝑇-periodic orbit.

The 6𝑇-periodic orbits are defined by duty cycle sequences (𝑑₁,𝑑₂,𝑑₃,𝑑₄,𝑑₅,𝑑₆) with four different values, where 𝑑₁=𝑑₃ and 𝑑₄=𝑑₆. Two possibilities for 10𝑇-periodic orbits are identified depending on the duty cycle sequence. Both options have four different values. The first has 𝑑₁=𝑑₃=𝑑₅, 𝑑₂=𝑑₄, and 𝑑₆=𝑑₇=𝑑₈=𝑑₉=𝑑₁₀, and the second has 𝑑₁=𝑑₃=𝑑₅, 𝑑₂=𝑑₄, 𝑑₇=𝑑₉, and 𝑑₆=𝑑₈=𝑑₁₀. The 11𝑇- and 22𝑇-periodic orbits are possible with four and five different values of the duty cycle, respectively.

The presence of multiple coexisting periodic orbits diminishes as ADC resolution increases. Ten different stable periodic orbits were detected in the fractal basin boundaries for 12-bit ADC, but only six coexisting periodic orbits were detected for the 16-bit ADC case. Additionally, the range of variation of the state variables becomes narrower as ADC resolution increases. The current is confined to the range (1.56, 1.66) for 8-bit ADC, to (1.596, 1.602) for 12-bit ADC, and to (1.5985, 1.5995) for 16-bit ADC.

Table 5 and Figure 8 summarize the dynamics found for 12-bit ADC resolution, while Table 6 and Figure 9 summarize the case for 16-bit ADC.

Table 5 

Examples of coexisting periodic orbits for 12-bit ADC resolution and 𝐾_𝑠=6.5. 𝐼_𝐿0=1.5.

Table 6 

Examples of coexisting periodic orbits for 16-bit ADC resolution and 𝐾_𝑠=6.5. 𝐼_𝐿0=1.5.

(a) Case 1—3 per

(b) Case 2—6 per

(c) Case 3—6 per

(d) Case 4—6 per

(e) Case 5—11 per

(f) Case 6—18 per

(g) Case 7—22 per

(h) Case 8—22 per

(i) Case 10—34 per

Figure 8 

Examples of coexisting periodic orbits for 12-bit ADC resolution and 𝐾𝑠=6.5. More analysis is presented in Table 5.

(a) Case 1—1 per

(b) Case 2—2 per

(c) Case 3—7 per

(d) Case 4—14 per

(e) Case 4—14 per

(f) Case 5—26 per

Figure 9 

Examples of coexisting periodic orbits for 16-bit ADC resolution and 𝐾𝑠=6.5. More analysis is presented in Table 6.

4. Conclusions

In this paper, the dynamic behavior of a DC-DC buck power converter controlled by the ZAD strategy when the ADC process is included in the modeling stage is analyzed. It has been shown that the dynamic behavior of the system with an ADC process has very important changes compared to the ideal system (without ADC). However, if 𝐾_𝑠>3.5 and depending on the application, 8-, 12- or 16-bit ADC resolutions are enough to reach 1𝑇 periodic orbit with low regulation error.

It has been determined that the ADC process has global consequences in the dynamical behavior of the system. Global phenomena such as the coexistence of periodic and aperiodic attractors, fractal basin boundaries, or transient chaos are exclusively caused by the A/D converters.

A route to chaos of the ZAD-controlled buck converter without an ADC process has been studied in many works [9, 10, 19]. In all works, this bifurcation scenario has been studied using local techniques based on the Jacobian matrix, the Lyapunov exponents, and the Floquet exponents. Smooth and nonsmooth bifurcations do not have a global incidence and the dynamics do not depend on initial conditions. Few results of the global dynamics can be obtained analytically due to the difficulty involved. Therefore, the numerical analysis for the global dynamics is usually the main approach [25].

We have numerically studied the quantization effects on chaos and periodic dynamics when the resolution of the A/D converters is varied in the set {8,12,16}. We have shown that these effects cannot be detected using statistical measures.

It has been detected that the doubling band transitions depend on ADC resolution. Only the transition from one-band chaos to two-band chaos is preserved for 8 bits, two-band transitions are preserved for 12 bits, and three-band transitions are preserved for 16 bits.

Band-merging process interrupted by cascades of periodic inclusions was detected.

Paradoxical behavior can be distinguished. The ADC process diminishes the presence of chaos dynamics, but the sensitivity to initial conditions strongly increases. Therefore, the long-term behaviors can be classified as high or very high periodic orbits, but fractal basin boundaries result in several possible long-term behaviors that depend heavily on initial value.

Period doubling route to chaos with an ideal ADC process is perturbed by quasiperiodic dynamics when ADC is included in the model. Other authors have studied the effects of ADC process in the dynamic behavior of the systems [11–14] and quasiperiodic route to chaos [27, 28], but as far as we know, the inclusion of quasiperiodic dynamics in route to chaos due to a quantization process has not been reported in the literature.

Acknowledgment

This work was partially supported by Vicerrectoría de Investigación, DIMA, Universidad Nacional de Colombia Sede Manizales, Project 12475.