Critical Delays in Clock Distribution Circuits

<table>Real positive values for <svg height="15.0875" id="M80" style="vertical-align:-2.3205pt" version="1.1" viewbox="0 0 34.049999 15.0875" width="34.049999" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> given in (<a href="https://static.hindawi.com/articles/mpe/volume-2013/145936/figures/#EEq19">19</a>). These values appear for <svg height="14.85" id="M81" style="vertical-align:-2.22495pt" version="1.1" viewbox="0 0 64.237503 14.85" width="64.237503" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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q0 45 -26.5 69.5t-68.5 24.5q-67 0 -120 -79l-20 20l43 63q51 56 127 56h1q66 0 107 -37t41 -95q0 -42 -31 -71q-22 -23 -68 -54z" id="x33"></path></g><g transform="matrix(.017,-0,0,-.017,38.956,12.012)"><path d="M574 449q-23 -58 -38 -79q-16 -4 -79 -4q-27 -100 -46 -219q-14 -87 7 -87t74 36l13 -27q-74 -81 -139 -81q-48 0 -48 62q0 22 8 59l60 258l-154 4q-21 -103 -54.5 -209t-64.5 -151q-38 -23 -83 -23l-7 15q46 36 94 152.5t64 216.5q-81 0 -138 -54l-18 23q22 27 39.5 43
t61.5 33.5t100 17.5q43 0 131.5 -2.5t129.5 -2.5q23 0 33.5 5t24.5 25z" id="x1D70B"></path></g><g transform="matrix(.017,-0,0,-.017,49.002,12.012)"><path d="M368 703l-264 -866h-60l265 866h59z" id="x2F"></path></g><g transform="matrix(.017,-0,0,-.017,56.005,12.012)"><path d="M456 178h-96v-72q0 -51 12.5 -62.5t72.5 -16.5v-27h-256v27q65 5 78 17t13 62v72h-260v28q182 271 300 426h40v-407h96v-47zM280 225v295h-2q-107 -148 -196 -295h198z" id="x34"></path></g>
</svg>.</table>

Mathematical Problems in Engineering

Critical Delays in Clock Distribution Circuits

Figure 1