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Mathematical Problems in Engineering
Volume 2013 (2013), Article ID 401616, 13 pages
A Generalized If-Then-Else Operator for the Representation of Multi-Output Functions
1School of Education, Tel-Aviv University, Ramat Aviv, Tel Aviv 69978, Israel
2School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel
Received 6 September 2012; Revised 30 December 2012; Accepted 22 January 2013
Academic Editor: Bozidar Sarler
Copyright © 2013 Ilya Levin and Osnat Keren. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- R. L. Ashenhurst, “The decomposition of switching functions,” in Procceedings of an International Symposium on the Theory of Switching, pp. 74–116, April 1957.
- G. de Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education,, 1994.
- J. P. Hayes, Introduction to Digital Logic Design, Addison-Wesley Longman Publishing, Boston, Mass, USA, 1993.
- M. G. Karpovsky, Finite Orthogonal Series in the Design of Digital Devices, John Wiley & Sons, New York, NY, USA, 1976.
- Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1970.
- E. J. McCluskey, Logic Design Principles, Prentice-Hall, Englewood Cliffs, NJ, USA, 1986.
- R. E. Miller, Switching Theory, John Wiley & Sons, New York, NY, USA, 1965.
- R. Brayton, “The future of logic synthesis and verification,” in Logic Synthesis and Verification, pp. 403–4434, Kluwer Academic Publishers, Norwell, Mass, USA, 2002.
- M. A. Perkowski, “A survey of literature on function decomposition,” Technical Report, GSRP Wright Laboratories, 1995.
- R. I. Bahar, E. A. Frohm, C. M. Gaona et al., “Algebraic decision diagrams and their applications,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 188–191, November 1993.
- C. M. Files and M. A. Perkowski, “New multivalued functional decomposition algorithms based on MDDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 9, pp. 1081–1086, 2000.
- Y. Iguchi, T. Sasao, and M. Matasuura, “Evaluation of multipleoutput logic functions using decision diagrams,” in Proceedings of the Asia and South Pacific Design Automation Conference, 2003.
- T. Sasao, Y. Iguchi, and M. Matsuura, “Comparison of decision diagrams for multiple-output functions,” in Proceedings of the International Workshop on Logic and Synthesis, 2002.
- S. N. Yanushkevich, D. M. Miller, V. P. Shmerko, and R. S. Stankovic, Decision Diagram Techniques For Micro- and Nanoelectronic Design Handbook, CRC Press, 2005.
- T. Sasao, Memory-Based Logic Synthesis, Springer, 2011.
- T. Sasao and M. Matsuura, “A method to decompose multiple-output logic functions,” in Proceedings of the 41st Design Automation Conference, pp. 428–433, San Diego, Calif, USA, June 2004.
- R. E. Bryant, “Symbolic boolean manipulation with ordered binary decision diagrams,” ACM Computing Surveys, vol. 24, no. 3, pp. 293–318, 1992.
- P. G. Hinman, Fundamentals of Mathematical Logic, A K Peters, 2005.
- G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publisher, 2005.
- S. Hassoun and T. Sasao, Eds., Logic Synthesis and Verification, vol. 654 of The Springer International Series in Engineering and Computer Science, 2002.
- S. Nagayama and T. Sasao, “Compact representations of logic functions using heterogeneous MDDs,” in Proceedings of the 33rd International Symposium on Multiple-Valued Logic, pp. 247–252, May 2003.
- T. Sasao, Switching Theory For Logic Synthesis, Kluwer Academic Publishers, 1999.
- T. Sasao and M. Fujita, Representations of Discrete Functions, Kluwer Academic Publishers, 1996.
- C. Baier and E. Clarke, “The algebraic Mu-calculus and MTBDDs,” in Proceedings of the 5th Workshop on Logic, Language, Information and Computation (WoLLIC '98), pp. 27–38, 1998.
- B. Chen and C. L. Lee, “Complement-based fast algorithm to generate universal test sets for multi-output functions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, pp. 370–377, 1994.
- R. Drechsler, J. Shi, and G. Fey, “Synthesis of fully testable circuits from BDDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 440–443, 2004.
- G. Fey and R. Drechsler, “Minimizing the number of paths in BDDs: theory and algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 4–11, 2006.
- W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1652–1663, 2006.
- M. G. Karpovsky, R. S. Stankovic, and J. T. Astola, “Reduction of sizes of decision diagrams by autocorrelation functions,” IEEE Transactions on Computers, vol. 52, no. 5, pp. 592–606, 2003.
- O. Keren, “Reduction of the average path length in binary decision diagrams by spectral methods,” IEEE Transactions on Computers, vol. 57, no. 4, pp. 520–531, 2008.
- O. Keren I. Levin and R. S. Stankovic, “Minimization of the number of paths in binary decision diagrams by using autocorrelation coefficients,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 31–44, 2011.
- C. Meinel, F. Somenzi, and T. Theobald, “Linear sifting of decision diagrams and its application synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 521–533, 2000.
- C. Yang and M. Ciesielski, “BDS: A BDD-based logic optimization system,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 866–876, 2002.
- S. Baranov, Logic and System Design of Digital Systems, TUT Press, 2008.
- I. Levin, O. Keren, V. Ostrovsky, and G. Kolotov, “Concurrent decomposition of multi-terminal BDDs,” pp. 165–169, Proceedings of the 7th International Workshop on Boolean Problems, Freiberg, Germany, September 2006.
- I. Levin and O. Keren, “Split multi-terminal binary decision diagrams,” in Proceedings of the 8th International Workshop on Boolean Problems, pp. 161–167, 2008.
- I. Levin and O. Keren, “Generalized if-then-else operator for compact polynomial representation of multi output functions,” in Proceedings of the 14th Euromicro Conference on Digital System Design (DSD '11), pp. 15–20, 2011.