Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

Table 3

The latency of the benchmark circuits achieved by the proposed approach compared with [8].

Benchmark	Latency (𝜇s)		Improvement (%)
	GLC [8]	The proposed model
[4-2-2]	108	108*	0
[5-2-2]	96	76*	20.83
[5-0-3]	138	132*	4.34
[ham3-D1]	286	185	35.31
[ham3-D2]	323	230	28.79
[mod5-D4]	228	162	28.94
[1bitAdder-rd32]	310	277	10.64
[10-0-2]	283	175	38.16
[7-0-3]	288	252	12.50
[13-1-3]	417	314	24.70

∗Optimal solution.