Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

<table>Problem area <svg height="13.0625" id="M397" style="vertical-align:-4.15506pt" version="1.1" viewbox="0 0 16.35 13.0625" width="16.35" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,7.825)"><path d="M559 271q0 -109 -83 -187t-189 -89l-36 -213q-16 -30 -86 -43l-7 9q10 36 53 242q-91 11 -139.5 63.5t-48.5 132.5q0 186 242 271l11 -28q-76 -34 -119.5 -91.5t-43.5 -136.5q0 -66 29 -108.5t77 -55.5q39 205 56 260q21 71 65 111t93 40q50 0 88 -45.5t38 -131.5z
M484 273q0 65 -26.5 99t-52.5 34q-37 0 -53 -75l-59 -298q80 5 135.5 74.5t55.5 165.5z" id="x1D711"></path></g>
<g transform="matrix(.012,-0,0,-.012,9.95,12.862)"><path d="M153 550l-26 -186q79 31 111 31q90 0 141.5 -51t51.5 -119q0 -93 -89 -166q-85 -69 -173 -71q-32 0 -61.5 11.5t-41.5 23.5q-18 17 -17 34q2 16 22 33q14 9 26 -1q61 -50 124 -50q60 0 93 43.5t33 104.5q0 69 -41.5 110t-121.5 41q-53 0 -102 -20l38 305h286l6 -8
l-26 -65h-233z" id="x35"></path></g>
</svg>, for nonpreemptive uniprocessor scheduling.</table>

Modelling and Simulation in Engineering

fig12

Figure 12

Figure 12: Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT 