Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

Table 3

Capsules used timer ports and messages.

Capsules	Timer ports	Protocols
Task generator	initial	trigger
Scheduler	Task A	Pa
	Task B	Pb
	Task C	Pc
	Task D	Pd
	Task E	Pe
	Task F	Pf
	Task G	Pg
	Task H	Ph
	Task I	Pi
	Task J	Pj
	Task K	Pk
	Task L	Pl
	Task M	Pm
	Task N	Pn
Processor	exetask1	pfree1