Abstract
A new graph-based symbolic technique (GBST) for deriving exact analytical expressions like the transfer function of an analog integrated circuit (IC), is introduced herein. The derived of a given analog IC is used to compute the frequency response bounds (maximum and minimum) associated to the magnitude and phase of , subject to some ranges of process variational parameters, and by performing nonlinear constrained optimization. Our simulations demonstrate the usefulness of the new GBST for deriving the exact symbolic expression for , and the last section highlights the good agreement between the frequency response bounds computed by our variational analysis approach versus traditional Monte Carlo simulations. As a conclusion, performing variational analysis using our proposed GBST for computing the frequency response bounds of analog ICs, shows a gain in computing time of 100x for a differential circuit topology and 50x for a 3-stage amplifier, compared to traditional Monte Carlo simulations.
1. Introduction
With the downscaling of the integrated circuit (IC) technology, nanometer circuit designs become more and more sensitive to process variations [1, 2], which are produced by fluctuations at the moment of manufacturing, and have been continuously increasing in relative magnitude as IC technology continues to scale to 45 nm and below. On the one hand, IC designers usually perform repeated Monte Carlo (MC) simulations to predict variations, leading to an expensive computational cost, while the main goal is computing the bounds of a given performance by varying the value of some parameters under certain percentage. On the other hand, to mitigate this drawback on performing repeated MC simulations, performance bound methods emerged as attractive techniques for variational analysis of analog ICs under parameter variations [3–7]. However, although those bound methods are quite efficient computing the lower and upper bounds of the magnitude and phase of a transfer function , systematic methods have not been proposed yet to obtain the variational symbolic expression for . Henceforth, this paper introduces a performance bound technique that derives the exact analytical of a linear (linearized) analog IC, as CMOS amplifiers, by applying a new graph-based symbolic technique (GBST), which is described in the next section. Afterwards, the frequency response bounds, for the magnitude and phase for of three amplifiers, are obtained by applying nonlinear constrained optimization.
2. Graph-Based Symbolic Technique
Symbolic analysis of analog circuits has been demonstrated to be useful for deriving analytical expressions such as [8–14]. An important contribution on the development of symbolic analysis techniques was the introduction of determinant decision diagrams (DDDs) [8, 9], whose advantage is computing symbolic expressions sharing many subexpressions [10, 11]. However, it was not realized for deriving exact analytical expressions for CMOS amplifiers [15]. That way, we introduce herein a new graph-based symbolic technique (GBST) for deriving exact symbolic expressions of analog ICs. Our proposed GBST exploits DDD concepts and has the advantage of being compact and unique as well.
2.1. Simple Case: Symbolic Determinant without Node Reuse
Let us consider the determinant given by (1) [9], of size . By applying GBST, the graph representation is built in a depth-first search (DFS) fashion, while one expects having paths of levels. Every element in the graph corresponds to a nonzero entry in . In this manner, one obtains the graph shown in Figure 1, where applying the rule of signs from Cramer’s rule (see (2)) does the assignation of signs to each node. A path is eliminated if a zero entry in the nodal admittance matrix is found. Consider
A tree in which arithmetic operations are encoded in the depth of the tree nodes represents the graph. That is, different depth implies multiplication and equal depth implies addition. This leads us to derive the expression:
2.2. Advanced Case: Symbolic Determinant with Node Reuse
In (3), the determinant is expressed as a sequence of products [8, 9], because the graph shown in Figure 1 does not reuse node information, while having many repetitive terms that correspond to the repeated minors and . For this case, the smallest the matrix minor, the highest the repetition rate. Therefore, our main idea is reusing the information of those repeated nodes. For example: , , and are product terms of minors in (1). In this manner, there are five two-nodded subgraphs with vertex sets , , , , and . As one sees, edges and are equivalents, so that subgraphs and carry the same information. In this case, node reuse is possible, and one just needs to identify node ancestors; for example, the subgraphs and have the node ancestors: for and for . Recall that each node is linked to a nonzero matrix entry; that is, . Node is in turn a representation of and of .
Extending node reuse in the whole graph, the first obvious consequence is that there are no repeated nodes; in other words, for a matrix with nonzero entries, there are nodes.
2.3. The Advanced Case in Detail
To derive the symbolic expression with node reuse, three different data structures are required. The first and most obvious is the node structure that contains the following:(i)node name: a unique name for each node, assigned as an index number;(ii)terms: an array containing the index and sign of the element;(iii)column: the column of the nonzero entry where the node belongs to;(iv)descendants: an array of node pointers linking to the descendants of the current node in the graph structure.
The second data structure is a graph type with the fields:(i)graph name: a unique name for the current graph. It is possible to have many different graphs; for example, to compute the transfer function , two graphs are required: one for deriving the numerator and the other for the denominator [9];(ii)matrix size: the size of the square matrix;(iii)root node: it is a trivial node with term value equal to 1 (see Figure 1) and row and column equal to zero. When multiple graphs are constructed (during factorization), the root node can be any of the nodes;(iv)visited columns: when traversing a graph to represent the determinant, the column of a visited node is appended to this array.
The third structure stores matrix elements and the independent vector.
From these structures, nodes are created. The row and column fields are used to evaluate the sign by (2) as well as to determine which nodes are to be skipped. The graph is generated starting with a trivial node named 0 with term value of 1; then the multiplication of terms is codified as the depth in the graph, and nodes are linked accordingly. The algorithm to build the graph structure for the representation of is sketched by Algorithm 1. Algorithm 2 computes the expression for the determinant. That way, the graph associated to the determinant in (1) is shown in Figure 2.
| ||||||||||||||||||||||||||||||||
| ||||||||
2.4. Symbol Factorization
Factorization takes place by executing Algorithm 3. The result is the expression as a polynomial that is represented by an array of sum of products with one entry for each power of symbol .
| ||||||||||||
Let us consider matrix in (4). To derive the polynomial form as powers of , the associated graph is shown in Figure 3, and the polynomial is given by (5). Consider
2.5. Applying the Graph-Based Symbolic Technique
Our proposed GBST starts off with an SPICE-like netlist as input. The allowed circuit elements are R, C, L, V, I, E, G, and M, being resistor, capacitor, inductor, independent voltage source, independent current source, voltage-controlled voltage source, voltage-controlled current source, and MOSFET. When formulating the equations, the symbol name is taken exactly as specified in the netlist, for example, R_name, C_name, M_name, and so forth. Their corresponding small-signal model based on controlled sources substitutes all active elements. In turn, controlled sources are modeled with combinations of norator and nullator in order to make use of the extensive studies on analysis of Nullor based circuits given in [9, 11, 14, 15]. The guidelines for obtaining the nodal admittance matrix by applying nodal analysis are summarized in [11]. Afterwards, applying our proposed graph-based symbolic technique derives the solution. In this manner, the computing information on the solutions for the common source amplifier, differential pair amplifier, three stages uncompensated OTA [15], recycled folded cascode OTA [16], and 741 opamp is listed in Table 1. Using the values computed by HSPICE, in order to verify correctness, does the numerical evaluation of the derived symbolic expression.
To demonstrate the suitability of the new graph-based symbolic technique (GBST), we performed a comparison with HSPICE and the DDD symbolic tool [3], as shown in Figure 4. As one sees, GBST is in good agreement with the numerical response computed by SPICE, while the DDD technique has an error around 10%. That way, GBST is applied herein to derive the exact analytical expression of CMOS amplifiers. The derived is used to perform variational analysis, in order to compute the frequency response bounds (maximum and minimum) of the magnitude and phase from , subject to some ranges of process variational parameters by performing nonlinear constrained optimization.
3. Constrained Optimization
To highlight the appropriateness of applying the new GBST in variational analysis for finding the lower and upper performance bounds for the magnitude and phase of an amplifier, we formulate a nonlinear constrained optimization problem. That way, we start from a transfer function, whose coefficients (e.g., and ) are obtained by our proposed graph-based symbolic technique in an s-expanded form; that is,
Notice that is a nonlinear function of . Furthermore, each parameter is a random variable with a variational range.
For , the nominal transfer function becomes
From it, one can obtain a variational transfer function with bounded magnitude and phase regions, which is described by [3]
where and are the lower and upper bounds of the magnitude, respectively, and and are the lower and upper bounds of the phase. The evaluation of (7) gives a complex valued result, where the magnitude and the phase angle are real values. The goal is to find the bounds of the magnitude and phase for , such that one can obtain (8). Henceforth, in the presence of process variations, the signal is perturbed from its nominal behavior, and it is usually bounded between its minimum and maximum limits, as sketched in Figure 5.
For instance, using the lower bound of the magnitude response at frequency , then the objective function is minimized and described by
In (9) represents the circuit parameters variable vector, subject to the optimization constraints . In IC design foundries and cell library vendors supply the constraints. Algorithm 4 summarizes this process.
| ||||||||||
3.1. A Simple Example in MATLAB
Let us consider Figure 6. In the frequency domain, capacitors and inductors are analyzed as complex impedances, and then the transfer function is given by
Assuming that and have variations of 20% from their nominal values and , then and . For this example, the iterative method called active set was used. As a result, three snapshots at different frequency points are shown in Figure 7.
3.2. Line Search Algorithm
A line search algorithm searches for a decrease in in a descent direction using the Armijo rule [17, 18] for stepsize control. The steplength is chosen to minimize along the ray , where is called the descent direction and the point is called , or even to just reduce “enough” [19]. That way, given the current point and descent direction , it looks for , such that
However, if the decreasing achieved by this inequality for some is too small, it is not possible to guarantee convergence to a local minimum. So in order to avoid this issue, must satisfy Armijo rule (sufficient decrease) given by where [20]. This is shown in Figure 8.
In Figure 8, the interval where (12) is accomplished is . We can rewrite this by (13) where the Armijo condition [18] to accept a trial point is given by (14), and is an integer greater than zero. If is rejected, the steplength is redefined by (15), where minimizes a quadratic model. This strategy of repeatedly testing sufficient decrease and reducing the stepsize if the test fails is called backtracking. The projected gradient (PGRAD) and spectral projected gradient (SPG) methods used herein for variational analysis of CMOS amplifiers are based on backtracking line search. Consider
3.3. Projected Gradient Method
The PGRAD method is described in [21]. It is the natural extension of the steepest descent algorithm [20], used in unconstrained optimization to bound constrained problems.
Given a current iterate , the new iterate is where the gradient is defined by
In (17), is a steplength parameter given by the Armijo rule, where one searches on a ray from in a direction where is locally decreasing [18]. Besides, in order to implement a line search scheme, one must specify what sufficient decrease means. Therefore, for bound constrained problems the sufficient decrease condition for line search is defined by where
In this case , where and , which is the smallest nonnegative integer such that there is sufficient decrease in . For the end condition, it is necessary to define the active and inactive sets. The set of constraints is called feasible set (), and a point in this set is a feasible point. Because the feasible set is compact, there is always a solution for this minimization problem. The th constraint is active at if either or . If the th constraint is not active, it is called inactive. Therefore, one can write and for the active and inactive sets, respectively. An active/inactive set is the set of indexes such that the th constraint is active/inactive. In this manner,
The stop criterion is given by (21), where and are relative and absolute tolerances. Consider
This optimization method is shown in Algorithm 5. It starts with and uses a sufficient decrease parameter and safeguarding parameters . Initially, . Given and the algorithm shows how to obtain and and when to stop the optimization engine.
| ||||||||||||||||||||||||
3.4. Spectral Projected Gradient Method
The SPG method improves choosing the steplength, which greatly speeds up the convergence of gradient methods [22]. Unlike the projected gradient method, the spectral projected gradient one [21] is more related to the quasi-Newton family [17]. The main idea behind the spectral choice of steplength is that the steepest descent method is very slow but it can be accelerated taking, instead of the stepsize that comes from the minimization of the function along the gradient of the current iteration, the one that comes from the one-dimensional minimization at the previous step.
The point in the first iteration of this method should be a feasible point; that is, the algorithm starts with and uses an integer , a small parameter , a large parameter , a sufficient decrease parameter , and safeguarding parameters . Consider .
The method is shown in Algorithm 6, where uses one-dimensional quadratic interpolation and it is safeguarded taking when the minimum of the one-dimensional quadratic lies outside . The line search condition in step 6 guarantees that the sequence remains in .
| ||||||||||||||||||||||||||||||
3.5. Remarks
The projected gradient and spectral projected gradient methods start at and use as search direction the internal projected gradient direction. In case of rejection of the first trial point, the next ones are computed along the same line. Also, for both methods, the calculation of uses a one-dimensional quadratic interpolation. Both algorithms involve a projection on the convex set , a function evaluation , and a gradient evaluation per iteration .
4. Simulation Results
The analog ICs for testing the variational methods PGRAD and SPG that use derived by the new GBST are shown in Figure 9. That way, after deriving the transfer function by applying the new GBST, and after setting the desired frequencies, the PGRAD and SPG methods are applied to find the magnitude and phase bounds for .
(a)
(b)
(c)
Both the PGRAD and SPG methods were programmed in C and compiled in an Ubuntu Linux environment with the GNU C compiler gcc-4.6.1, with 4 GB RAM in an Intel Core i3. The performance bounds results for the differential pair are shown in Figure 10 and for the 3-stage OTA in Figure 11. The lines in blue are those corresponding to Monte Carlo simulations, which are well bounded by the bounds computed by the variational methods PGRAD and SPG. Table 2 summarizes the results where it can be appreciated that both variational methods show better times than by performing repeated Monte Carlo simulations when using HSPICE.
(a)
(b)
(a)
(b)
5. Conclusions
A new graph-based symbolic technique (GBST) for deriving exact analytical expressions for analog ICs, such as , and whose symbolic expressions are used to perform variational analysis to obtain performance frequency bounds has been introduced. The variational analysis needs as input the computed by applying our proposed GBST, and it was based on nonlinear constrained optimization using two line search methods, namely, projected gradient (PGRAD) and spectral projected gradient (SPG).
It was demonstrated that the bound analysis based on GBST is suitable for analog ICs. In addition, the time computation of PGRAD and SPG for obtaining the frequency response bounds of analog ICs was improved with respect to HSPICE, when performing repeated Monte Carlo simulations. As shown in the last section, computing the frequency response bounds by using GBST showed a gain of 100x for the differential pair and 50x for the 3-stage amplifier, compared to repeated Monte Carlo simulations, thus justifying the usefulness of using GBST.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgments
This project is partially supported by CONACyT and UC-MEXUS-CONACYT under projects 131839-Y and CN-11-575.