An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Table 3

Comparison of parameters of Asynchronous Viterbi decoder with the state of art from existing designs [19].

Parameters	Synchronous design	Asynchronous design	Asynchronous design	Asynchronous QDI design
Technology	0.25 um	0.35 um	0.18 um	180 nm
No. of states	64	64	64	64
Code rate
Max Speed	200 Mb/s	90 Mb/s	213 Mb/s	433 Mb/s
Avg. Power	183 mW	1333 mW	85 mW	74.03 mW