The Scientific World Journal: Electronics http://www.hindawi.com The latest articles from Hindawi Publishing Corporation © 2014 , Hindawi Publishing Corporation . All rights reserved. Experimental Realization of a Multiscroll Chaotic Oscillator with Optimal Maximum Lyapunov Exponent Wed, 16 Apr 2014 10:28:03 +0000 http://www.hindawi.com/journals/tswj/2014/303614/ Nowadays, different kinds of experimental realizations of chaotic oscillators have been already presented in the literature. However, those realizations do not consider the value of the maximum Lyapunov exponent, which gives a quantitative measure of the grade of unpredictability of chaotic systems. That way, this paper shows the experimental realization of an optimized multiscroll chaotic oscillator based on saturated function series. First, from the mathematical description having four coefficients (a, b, c, d1), an optimization evolutionary algorithm varies them to maximize the value of the positive Lyapunov exponent. Second, a realization of those optimized coefficients using operational amplifiers is given. Herein a, b, c, d1 are implemented with precision potentiometers to tune up to four decimals of the coefficients having the range between 0.0001 and 1.0000. Finally, experimental results of the phase-space portraits for generating from 2 to 10 scrolls are listed to show that their associated value for the optimal maximum Lyapunov exponent increases by increasing the number of scrolls, thus guaranteeing a more complex chaotic behavior. Esteban Tlelo-Cuautle, Ana Dalia Pano-Azucena, Victor Hugo Carbajal-Gomez, and Mauro Sanchez-Sanchez Copyright © 2014 Esteban Tlelo-Cuautle et al. All rights reserved. Analysis of Glass-Reinforced Epoxy Material for Radio Frequency Resonator Sun, 06 Apr 2014 12:54:25 +0000 http://www.hindawi.com/journals/tswj/2014/831435/ A radio frequency (RF) resonator using glass-reinforced epoxy material for C and X band is proposed in this paper. Microstrip line technology for RF over glass-reinforced epoxy material is analyzed. Coupling mechanism over RF material and parasitic coupling performance is explained utilizing even and odd mode impedance with relevant equivalent circuit. Babinet’s principle is deployed to explicate the circular slot ground plane of the proposed resonator. The resonator is designed over four materials from different backgrounds which are glass-reinforced epoxy, polyester, gallium arsenide (GaAs), and rogers RO 4350B. Parametric studies and optimization algorithm are applied over the geometry of the microstrip resonator to achieve dual band response for C and X band. Resonator behaviors for different materials are concluded and compared for the same structure. The final design is fabricated over glass-reinforced epoxy material. The fabricated resonator shows a maximum directivity of 5.65 dBi and 6.62 dBi at 5.84 GHz and 8.16 GHz, respectively. The lowest resonance response is less than −20 dB for C band and −34 dB for X band. The resonator is prototyped using LPKF (S63) drilling machine to study the material behavior. M. R. Zaman, M. T. Islam, N. Misran, and Baharudin Yatim Copyright © 2014 M. R. Zaman et al. All rights reserved. Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications Wed, 19 Mar 2014 13:10:14 +0000 http://www.hindawi.com/journals/tswj/2014/523429/ Modern pixel detectors, particularly those designed and constructed for applications and experiments for high-energy physics, are commonly built implementing general readout architectures, not specifically optimized in terms of speed. High-energy physics experiments use bidimensional matrices of sensitive elements located on a silicon die. Sensors are read out via other integrated circuits bump bonded over the sensor dies. The speed of the readout electronics can significantly increase the overall performance of the system, and so here novel forms of readout architectures are studied and described. These circuits have been investigated in terms of speed and are particularly suited for large monolithic, low-pitch pixel detectors. The idea is to have a small simple structure that may be expanded to fit large matrices without affecting the layout complexity of the chip, while maintaining a reasonably high readout speed. The solutions might be applied to devices for applications not only in physics but also to general-purpose pixel detectors whenever online fast data sparsification is required. The paper presents also simulations on the efficiencies of the systems as proof of concept for the proposed ideas. A. Gabrielli Copyright © 2014 A. Gabrielli. All rights reserved. Single-Event-Upset Sensitivity Analysis on Low-Swing Drivers Wed, 19 Mar 2014 09:02:05 +0000 http://www.hindawi.com/journals/tswj/2014/876435/ Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but results in increase of power dissipation. Subsequently, other alternatives are considered. The impact of transistor sizes and temperature on SEU tolerance is tested. Results indicate no significant changes in when the effective transistor length is increased by 10%, but there is an improvement when high temperature and high bias currents are applied. However, this is due to other process parameters that are temperature dependent, which contribute to the sharp increase in . It is found that, with temperature, there is no clear factor that can justify the direct impact of temperature on the SEU tolerance. Thus, in order to improve the SEU tolerance, high bias currents are still considered to be the most effective method in improving the SEU sensitivity. However, good trade-off is required for the low-swing driver in order to meet the reliability target with minimal power overhead. Nor Muzlifah Mahyuddin and Gordon Russell Copyright © 2014 Nor Muzlifah Mahyuddin and Gordon Russell. All rights reserved. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor Mon, 17 Mar 2014 16:48:56 +0000 http://www.hindawi.com/journals/tswj/2014/963709/ This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. Mohammad Reza Shokrani, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie Copyright © 2014 Mohammad Reza Shokrani et al. All rights reserved. A Real-Time and Closed-Loop Control Algorithm for Cascaded Multilevel Inverter Based on Artificial Neural Network Sun, 16 Mar 2014 11:25:21 +0000 http://www.hindawi.com/journals/tswj/2014/508163/ In order to control the cascaded H-bridges (CHB) converter with staircase modulation strategy in a real-time manner, a real-time and closed-loop control algorithm based on artificial neural network (ANN) for three-phase CHB converter is proposed in this paper. It costs little computation time and memory. It has two steps. In the first step, hierarchical particle swarm optimizer with time-varying acceleration coefficient (HPSO-TVAC) algorithm is employed to minimize the total harmonic distortion (THD) and generate the optimal switching angles offline. In the second step, part of optimal switching angles are used to train an ANN and the well-designed ANN can generate optimal switching angles in a real-time manner. Compared with previous real-time algorithm, the proposed algorithm is suitable for a wider range of modulation index and results in a smaller THD and a lower calculation time. Furthermore, the well-designed ANN is embedded into a closed-loop control algorithm for CHB converter with variable direct voltage (DC) sources. Simulation results demonstrate that the proposed closed-loop control algorithm is able to quickly stabilize load voltage and minimize the line current’s THD (<5%) when subjecting the DC sources disturbance or load disturbance. In real design stage, a switching angle pulse generation scheme is proposed and experiment results verify its correctness. Libing Wang, Chengxiong Mao, Dan Wang, Jiming Lu, Junfeng Zhang, and Xun Chen Copyright © 2014 Libing Wang et al. All rights reserved. A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product Thu, 27 Feb 2014 16:14:40 +0000 http://www.hindawi.com/journals/tswj/2014/453675/ The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. Kunwar Singh, Satish Chandra Tiwari, and Maneesha Gupta Copyright © 2014 Kunwar Singh et al. All rights reserved. A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters Tue, 25 Feb 2014 06:56:01 +0000 http://www.hindawi.com/journals/tswj/2014/521717/ A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively. Bo Zhou Copyright © 2014 Bo Zhou. All rights reserved. High Isolation Single-Pole Four-Throw RF MEMS Switch Based on Series-Shunt Configuration Sun, 23 Feb 2014 14:08:58 +0000 http://www.hindawi.com/journals/tswj/2014/605894/ This paper presents a novel design of single-pole four-throw (SP4T) RF-MEMS switch employing both capacitive and ohmic switches. It is designed on high-resistivity silicon substrate and has a compact area of 1.06 mm2. The series or ohmic switches have been designed to provide low insertion loss with good ohmic contact. The pull-in voltage for ohmic switches is calculated to be 7.19 V. Shunt or capacitive switches have been used in each port to improve the isolation for higher frequencies. The proposed SP4T switch provides excellent RF performances with isolation better than 70.64 dB and insertion loss less than 0.72 dB for X-band between the input port and each output port. Tejinder Singh and Navjot Khaira Copyright © 2014 Tejinder Singh and Navjot Khaira. All rights reserved. 100 nm AlSb/InAs HEMT for Ultra-Low-Power Consumption, Low-Noise Applications Sun, 23 Feb 2014 13:17:02 +0000 http://www.hindawi.com/journals/tswj/2014/136340/ We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. Extrinsic cut-off frequencies of 100/125 GHz together with minimum noise figure  dB and associated gain  dB at 12 GHz have been obtained at drain bias of only 80 mV, corresponding to 4 mW/mm DC power dissipation. This demonstrates the great ability of AlSb/InAs HEMT for high-frequency operation combined with low-noise performances in ultra-low-power regime. Cyrille Gardès, Sonia Bagumako, Ludovic Desplanque, Nicolas Wichmann, Sylvain Bollaert, François Danneville, Xavier Wallart, and Yannick Roelens Copyright © 2014 Cyrille Gardès et al. All rights reserved. Continuous-Time ADC with Implicit Variable Gain Amplifier for CMOS Image Sensor Tue, 18 Feb 2014 11:44:08 +0000 http://www.hindawi.com/journals/tswj/2014/208540/ This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency. Fang Tang, Amine Bermak, Amira Abbes, and Mohieddine Amor Benammar Copyright © 2014 Fang Tang et al. All rights reserved. SFG Synthesis of General High-Order All-Pass and All-Pole Current Transfer Functions Using CFTAs Tue, 11 Feb 2014 09:02:17 +0000 http://www.hindawi.com/journals/tswj/2014/271926/ An approach of using the signal flow graph (SFG) technique to synthesize general high-order all-pass and all-pole current transfer functions with current follower transconductance amplifiers (CFTAs) and grounded capacitors has been presented. For general nth-order systems, the realized all-pass structure contains at most n + 1 CFTAs and n grounded capacitors, while the all-pole lowpass circuit requires only n CFTAs and n grounded capacitors. The resulting circuits obtained from the synthesis procedure are resistor-less structures and especially suitable for integration. They also exhibit low-input and high-output impedances and also convenient electronic controllability through the -value of the CFTA. Simulation results using real transistor model parameters ALA400 are also included to confirm the theory. Worapong Tangsrirat Copyright © 2014 Worapong Tangsrirat. All rights reserved. Analysis of Paralleling Limited Capacity Voltage Sources by Projective Geometry Method Mon, 10 Feb 2014 12:13:09 +0000 http://www.hindawi.com/journals/tswj/2014/359893/ The droop current-sharing method for voltage sources of a limited capacity is considered. Influence of equalizing resistors and load resistor is investigated on uniform distribution of relative values of currents when the actual loading corresponds to the capacity of a concrete source. Novel concepts for quantitative representation of operating regimes of sources are entered with use of projective geometry method. Alexandr Penin Copyright © 2014 Alexandr Penin. All rights reserved. Multiple Chaos Synchronization System for Power Quality Classification in a Power System Mon, 10 Feb 2014 00:00:00 +0000 http://www.hindawi.com/journals/tswj/2014/902167/ This document proposes multiple chaos synchronization (CS) systems for power quality (PQ) disturbances classification in a power system. Chen-Lee based CS systems use multiple detectors to track the dynamic errors between the normal signal and the disturbance signal, including power harmonics, voltage fluctuation phenomena, and voltage interruptions. Multiple detectors are used to monitor the dynamic errors between the master system and the slave system and are used to construct the feature patterns from time-domain signals. The maximum likelihood method (MLM), as a classifier, performs a comparison of the patterns of the features in the database. The proposed method can adapt itself without the need for adjustment of parameters or iterative computation. For a sample power system, the test results showed accurate discrimination, good robustness, and faster processing time for the detection of PQ disturbances. Cong-Hui Huang and Chia-Hung Lin Copyright © 2014 Cong-Hui Huang and Chia-Hung Lin. All rights reserved. A Dual-Mode Bandpass Filter with Multiple Controllable Transmission-Zeros Using T-Shaped Stub-Loaded Resonators Sun, 09 Feb 2014 13:48:05 +0000 http://www.hindawi.com/journals/tswj/2014/572360/ A dual-mode broadband bandpass filter (BPF) with multiple controllable transmission-zeros using T-shaped stub-loaded resonators (TSSLRs) is presented. Due to the symmetrical plane, the odd-even-mode theory can be adopted to characterize the BPF. The proposed filter consists of a dual-mode TSSLR and two modified feed-lines, which introduce two capacitive and inductive source-load (S-L) couplings. Five controllable transmission zeros (TZs) can be achieved for the high selectivity and the wide stopband because of the tunable amount of coupling capacitance and inductance. The center frequency of the proposed BPF is 5.8 GHz, with a 3 dB fraction bandwidth of 8.9%. The measured insertion and return losses are 1.75 and 28.18 dB, respectively. A compact size and second harmonic frequency suppression can be obtained by the proposed BPF with S-L couplings. Zh. Yao, C. Wang, and N. Y. Kim Copyright © 2014 Zh. Yao et al. All rights reserved. A Novel High-Power Dual-Band Coupled-Line Gysel Power Divider with Impedance-Transforming Functions Sun, 09 Feb 2014 10:21:58 +0000 http://www.hindawi.com/journals/tswj/2014/831073/ A novel coupled-line structure is proposed to design dual-band and high-power Gysel power dividers with inherent impedance-transforming functions. Based on traditional even- and odd-mode technique, the analytical design methods in closed-form formula are obtained and the accurate electrical parameters analysis is presented. Due to the usage of coupled-line sections, more design-parameter freedom and a wider frequency-ratio operation range for this kind of dual-band Gysel powder divider are obtained. Several numerical examples are designed and calculated to demonstrate flexible dual-band applications with different impedance-transforming functions. A practical microstrip power divider operating at 2 GHz and 3.2 GHz is designed, fabricated, and measured. The good agreement between the calculated and measured results verifies our proposed circuit structure and analytical design approach. Weimin Wang, Yongle Wu, and Yuanan Liu Copyright © 2014 Weimin Wang et al. All rights reserved. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair Thu, 06 Feb 2014 12:48:50 +0000 http://www.hindawi.com/journals/tswj/2014/421321/ This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity. Ilias Chlis, Domenico Pepe, and Domenico Zito Copyright © 2014 Ilias Chlis et al. All rights reserved. Detection of Lungs Status Using Morphological Complexities of Respiratory Sounds Thu, 06 Feb 2014 08:40:58 +0000 http://www.hindawi.com/journals/tswj/2014/182938/ Traditionally, the clinical diagnosis of a respiratory disease is made from a careful clinical examination including chest auscultation. Objective analysis and automatic interpretation of the lung sound based on its physical characters are strongly warranted to assist clinical practice. In this paper, a new method is proposed to distinguish between the normal and the abnormal subjects using the morphological complexities of the lung sound signals. The morphological embedded complexities used in these experiments have been calculated in terms of texture information (lacunarity), irregularity index (sample entropy), third order moment (skewness), and fourth order moment (Kurtosis). These features are extracted from a mixed data set of 10 normal and 20 abnormal subjects and are analyzed using two different classifiers: extreme learning machine (ELM) and support vector machine (SVM) network. The results are obtained using 5-fold cross-validation. The performance of the proposed method is compared with a wavelet analysis based method. The developed algorithm gives a better accuracy of 92.86% and sensitivity of 86.30% and specificity of 86.90% for a composite feature vector of four morphological indices. Ashok Mondal, Parthasarathi Bhattacharya, and Goutam Saha Copyright © 2014 Ashok Mondal et al. All rights reserved. Frequency Selective Properties of Coaxial Transmission Lines Loaded with Combined Artificial Inclusions Thu, 23 Jan 2014 00:00:00 +0000 http://www.hindawi.com/journals/tswj/2014/731947/ The properties of a modified coaxial transmission line by periodic inclusions will be discussed. The introduction of split ring resonators, conductor stubs, air gaps, and combination of these gives rise to new frequency selective properties, such as stopband or passband behavior, observable in planar as well as volumetric metamaterial structures. These results envisage new potential applications and implementation of devices in coaxial transmission line technology. Francisco Falcone and Javier Gil Copyright © 2014 Francisco Falcone and Javier Gil. All rights reserved. Designing a Ring-VCO for RFID Transponders in 0.18 m CMOS Process Wed, 22 Jan 2014 11:41:30 +0000 http://www.hindawi.com/journals/tswj/2014/580385/ In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. Jubayer Jalil, Mamun Bin Ibne Reaz, Mohammad Arif Sobhan Bhuiyan, Labonnah Farzana Rahman, and Tae Gyu Chang Copyright © 2014 Jubayer Jalil et al. All rights reserved. Tunable First-Order Resistorless All-Pass Filter with Low Output Impedance Wed, 22 Jan 2014 11:09:50 +0000 http://www.hindawi.com/journals/tswj/2014/219453/ This paper presents a voltage mode cascadable single active element tunable first-order all-pass filter with a single passive component. The active element used to realise the filter is a new building block termed as differential difference dual-X current conveyor with a buffered output (DD-DXCCII). The filter is thus realized with the help of a DD-DXCCII, a capacitor, and a MOS transistor. By exploiting the low output impedance, a higher order filter is also realized. Nonideal and parasitic study is also carried out on the realised filters. The proposed DD-DXCCII filters are simulated using TSMC the 0.25 µm technology. Parveen Beg Copyright © 2014 Parveen Beg. All rights reserved. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor Wed, 22 Jan 2014 10:23:31 +0000 http://www.hindawi.com/journals/tswj/2014/861278/ Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample. Fang Tang, Amine Bermak, Abbes Amira, Mohieddine Amor Benammar, Debiao He, and Xiaojin Zhao Copyright © 2014 Fang Tang et al. All rights reserved. Robust Range Estimation with a Monocular Camera for Vision-Based Forward Collision Warning System Thu, 16 Jan 2014 12:04:49 +0000 http://www.hindawi.com/journals/tswj/2014/923632/ We propose a range estimation method for vision-based forward collision warning systems with a monocular camera. To solve the problem of variation of camera pitch angle due to vehicle motion and road inclination, the proposed method estimates virtual horizon from size and position of vehicles in captured image at run-time. The proposed method provides robust results even when road inclination varies continuously on hilly roads or lane markings are not seen on crowded roads. For experiments, a vision-based forward collision warning system has been implemented and the proposed method is evaluated with video clips recorded in highway and urban traffic environments. Virtual horizons estimated by the proposed method are compared with horizons manually identified, and estimated ranges are compared with measured ranges. Experimental results confirm that the proposed method provides robust results both in highway and in urban traffic environments. Ki-Yeong Park and Sun-Young Hwang Copyright © 2014 Ki-Yeong Park and Sun-Young Hwang. All rights reserved. High-Speed Current dq PI Controller for Vector Controlled PMSM Drive Thu, 16 Jan 2014 09:37:34 +0000 http://www.hindawi.com/journals/tswj/2014/709635/ High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. Mohammad Marufuzzaman, Mamun Bin Ibne Reaz, Labonnah Farzana Rahman, and Tae Gyu Chang Copyright © 2014 Mohammad Marufuzzaman et al. All rights reserved. Robust Human Machine Interface Based on Head Movements Applied to Assistive Robotics Thu, 26 Dec 2013 15:30:58 +0000 http://www.hindawi.com/journals/tswj/2013/589636/ This paper presents an interface that uses two different sensing techniques and combines both results through a fusion process to obtain the minimum-variance estimator of the orientation of the user’s head. Sensing techniques of the interface are based on an inertial sensor and artificial vision. The orientation of the user’s head is used to steer the navigation of a robotic wheelchair. Also, a control algorithm for assistive technology system is presented. The system is evaluated by four individuals with severe motors disability and a quantitative index was developed, in order to objectively evaluate the performance. The results obtained are promising since most users could perform the proposed tasks with the robotic wheelchair. Elisa Perez, Natalia López, Eugenio Orosco, Carlos Soria, Vicente Mut, and Teodiano Freire-Bastos Copyright © 2013 Elisa Perez et al. All rights reserved. Electricity Usage Scheduling in Smart Building Environments Using Smart Devices Thu, 26 Dec 2013 14:19:07 +0000 http://www.hindawi.com/journals/tswj/2013/468097/ With the recent advances in smart grid technologies as well as the increasing dissemination of smart meters, the electricity usage of every moment can be detected in modern smart building environments. Thus, the utility company adopts different price of electricity at each time slot considering the peak time. This paper presents a new electricity usage scheduling algorithm for smart buildings that adopts real-time pricing of electricity. The proposed algorithm detects the change of electricity prices by making use of a smart device and changes the power mode of each electric device dynamically. Specifically, we formulate the electricity usage scheduling problem as a real-time task scheduling problem and show that it is a complex search problem that has an exponential time complexity. An efficient heuristic based on genetic algorithms is performed on a smart device to cut down the huge searching space and find a reasonable schedule within a feasible time budget. Experimental results with various building conditions show that the proposed algorithm reduces the electricity charge of a smart building by 25.6% on average and up to 33.4%. Eunji Lee and Hyokyung Bahn Copyright © 2013 Eunji Lee and Hyokyung Bahn. All rights reserved. Substrate Integrated Waveguide Cross-Coupling Filter with Multilayer Hexagonal Cavity Wed, 25 Dec 2013 10:52:39 +0000 http://www.hindawi.com/journals/tswj/2013/682707/ Hexagonal cavities and their applications to multilayer substrate integrated waveguide (SIW) filters are presented. The hexagonal SIW cavity which can combine flexibility of rectangular one and performance of circular one is convenient for bandpass filter’s design. Three types of experimental configuration with the same central frequency of 10 GHz and bandwidth of 6%, including three-order and four-order cross-coupling topologies, are constructed and fabricated based on low temperature cofired ceramic (LTCC) technology. Both theoretical and experimental results are presented. B. Wu, Z. Q. Xu, and J. X. Liao Copyright © 2013 B. Wu et al. All rights reserved. New Power Sharing Control for Inverter-Dominated Microgrid Based on Impedance Match Concept Mon, 23 Dec 2013 19:07:01 +0000 http://www.hindawi.com/journals/tswj/2013/816525/ Power flow control is one of the most important issues for operating the inverter-dominated autonomous microgrid. A technical challenge is how to achieve the accurate active/reactive power sharing of inverters. and droop control schemes have been widely used for power sharing in the past decades. But they suffer from the poor power sharing in the presence of unequal line impedance. In order to solve the problem, a comprehensive analysis of the power droop control is presented, and a new droop control based on the impedance match concept is proposed in this paper. In addition, the design guidelines of control coefficients and virtual impedance are provided. Finally, the performance evaluation is carried out, and the evaluation results verify the effectiveness of the proposed method. Herong Gu, Deyu Wang, Hong Shen, Wei Zhao, and Xiaoqiang Guo Copyright © 2013 Herong Gu et al. All rights reserved. Comparison between Phase-Shift Full-Bridge Converters with Noncoupled and Coupled Current-Doubler Rectifier Thu, 05 Dec 2013 15:51:09 +0000 http://www.hindawi.com/journals/tswj/2013/621896/ This paper presents comparison between phase-shift full-bridge converters with noncoupled and coupled current-doubler rectifier. In high current capability and high step-down voltage conversion, a phase-shift full-bridge converter with a conventional current-doubler rectifier has the common limitations of extremely low duty ratio and high component stresses. To overcome these limitations, a phase-shift full-bridge converter with a noncoupled current-doubler rectifier (NCDR) or a coupled current-doubler rectifier (CCDR) is, respectively, proposed and implemented. In this study, performance analysis and efficiency obtained from a 500 W phase-shift full-bridge converter with two improved current-doubler rectifiers are presented and compared. From their prototypes, experimental results have verified that the phase-shift full-bridge converter with NCDR has optimal duty ratio, lower component stresses, and output current ripple. In component count and efficiency comparison, CCDR has fewer components and higher efficiency at full load condition. For small size and high efficiency requirements, CCDR is relatively suitable for high step-down voltage and high efficiency applications. Cheng-Tao Tsai, Jye-Chau Su, and Sheng-Yu Tseng Copyright © 2013 Cheng-Tao Tsai et al. All rights reserved. Current Conveyor All-Pass Sections: Brief Review and Novel Solution Thu, 28 Nov 2013 12:00:42 +0000 http://www.hindawi.com/journals/tswj/2013/429391/ This study relates to the review of an important analog electronic function in form of all-pass filter’s realization using assorted current conveyor types and their relative performances, which resulted in a novel solution based on a new proposed active element. The study encompasses notable proposals during last the decade or more, and provides a platform for a broader future survey on the topic for enhancing the knowledge penetration amongst the researchers in the specified field. A new active element named EXCCII (Extra-X second generation current conveyor) with buffered output is found in the study along with its use in a new first-order all-pass section, with possible realization using commercially available IC (AD-844) and results. Sudhanshu Maheshwari Copyright © 2013 Sudhanshu Maheshwari. All rights reserved. Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier Thu, 28 Nov 2013 10:48:04 +0000 http://www.hindawi.com/journals/tswj/2013/201565/ This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells () as core circuits. The advantage of this element is that the current transfer ratios ( and ) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated. Worapong Tangsrirat Copyright © 2013 Worapong Tangsrirat. All rights reserved. A Robust Variable Sampling Time BLDC Motor Control Design Based upon -Synthesis Tue, 12 Nov 2013 08:38:50 +0000 http://www.hindawi.com/journals/tswj/2013/236404/ The variable sampling rate system is encountered in many applications. When the speed information is derived from the position marks along the trajectory, one would have a speed dependent sampling rate system. The conventional fixed or multisampling rate system theory may not work in these cases because the system dynamics include the uncertainties which resulted from the variable sampling rate. This paper derived a convenient expression for the speed dependent sampling rate system. The varying sampling rate effect is then translated into multiplicative uncertainties to the system. The design then uses the popular -synthesis process to achieve a robust performance controller design. The implementation on a BLDC motor demonstrates the effectiveness of the design approach. Chung-Wen Hung and Jia-Yush Yen Copyright © 2013 Chung-Wen Hung and Jia-Yush Yen. All rights reserved. A Compact Symmetric Microstrip Filter Based on a Rectangular Meandered-Line Stepped Impedance Resonator with a Triple-Band Bandstop Response Mon, 11 Nov 2013 15:16:48 +0000 http://www.hindawi.com/journals/tswj/2013/457693/ This paper presents a symmetric-type microstrip triple-band bandstop filter incorporating a tri-section meandered-line stepped impedance resonator (SIR). The length of each section of the meandered line is 0.16, 0.15, and 0.83 times the guided wavelength (), so that the filter features three stop bands at 2.59 GHz, 6.88 GHz, and 10.67 GHz, respectively. Two symmetric SIRs are employed with a microstrip transmission line to obtain wide bandwidths of 1.12, 1.34, and 0.89 GHz at the corresponding stop bands. Furthermore, an equivalent circuit model of the proposed filter is developed, and the model matches the electromagnetic simulations well. The return losses of the fabricated filter are measured to be −29.90 dB, −28.29 dB, and −26.66 dB while the insertion losses are 0.40 dB, 0.90 dB, and 1.10 dB at the respective stop bands. A drastic reduction in the size of the filter was achieved by using a simplified architecture based on a meandered-line SIR. Rajendra Dhakal and Nam-Young Kim Copyright © 2013 Rajendra Dhakal and Nam-Young Kim. All rights reserved. Approximate Single-Diode Photovoltaic Model for Efficient I-V Characteristics Estimation Tue, 05 Nov 2013 16:43:29 +0000 http://www.hindawi.com/journals/tswj/2013/230471/ Precise photovoltaic (PV) behavior models are normally described by nonlinear analytical equations. To solve such equations, it is necessary to use iterative procedures. Aiming to make the computation easier, this paper proposes an approximate single-diode PV model that enables high-speed predictions for the electrical characteristics of commercial PV modules. Based on the experimental data, statistical analysis is conducted to validate the approximate model. Simulation results show that the calculated current-voltage (I-V) characteristics fit the measured data with high accuracy. Furthermore, compared with the existing modeling methods, the proposed model reduces the simulation time by approximately 30% in this work. Jieming Ma, Ka Lok Man, T. O. Ting, Nan Zhang, Sheng-Uei Guan, and Prudence W. H. Wong Copyright © 2013 Jieming Ma et al. All rights reserved. Control of Disturbing Loads in Residential and Commercial Buildings via Geometric Algebra Wed, 23 Oct 2013 14:53:53 +0000 http://www.hindawi.com/journals/tswj/2013/463983/ Many definitions have been formulated to represent nonactive power for distorted voltages and currents in electronic and electrical systems. Unfortunately, no single universally suitable representation has been accepted as a prototype for this power component. This paper defines a nonactive power multivector from the most advanced multivectorial power theory based on the geometric algebra (GA). The new concept can have more importance on harmonic loads compensation, identification, and metering, between other applications. Likewise, this paper is concerned with a pioneering method for the compensation of disturbing loads. In this way, we propose a multivectorial relative quality index   associated with the power multivector. It can be assumed as a new index for power quality evaluation, harmonic sources detection, and power factor improvement in residential and commercial buildings. The proposed method consists of a single-point strategy based of a comparison among different relative quality index multivectors, which may be measured at the different loads on the same metering point. The comparison can give pieces of information with magnitude, direction, and sense on the presence of disturbing loads. A numerical example is used to illustrate the clear capabilities of the suggested approach. Manuel-V. Castilla Copyright © 2013 Manuel-V. Castilla. All rights reserved. Design of UWB Monopole Antenna with Dual Notched Bands Using One Modified Electromagnetic-Bandgap Structure Thu, 19 Sep 2013 17:05:06 +0000 http://www.hindawi.com/journals/tswj/2013/917965/ A modified electromagnetic-bandgap (M-EBG) structure and its application to planar monopole ultra-wideband (UWB) antenna are presented. The proposed M-EBG which comprises two strip patch and an edge-located via can perform dual notched bands. By properly designing and placing strip patch near the feedline, the proposed M-EBG not only possesses a simple structure and compact size but also exhibits good band rejection. Moreover, it is easy to tune the dual notched bands by altering the dimensions of the M-EBG. A demonstration antenna with dual band-notched characteristics is designed and fabricated to validate the proposed method. The results show that the proposed antenna can satisfy the requirements of VSWR < 2 over UWB 3.1–10.6 GHz, except for the rejected bands of the world interoperability for microwave access (WiMAX) and the wireless local area network (WLAN) at 3.5 GHz and 5.5 GHz, respectively. Hao Liu and Ziqiang Xu Copyright © 2013 Hao Liu and Ziqiang Xu. All rights reserved. Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range Wed, 18 Sep 2013 15:58:58 +0000 http://www.hindawi.com/journals/tswj/2013/373429/ The carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in 180 nm CMOS for high reconfiguration. The proposed architecture achieves wide CF range of 2 M–1 GHz, high power efficiency of 70%, and low error vector magnitude (EVM) of 3%, with spectrum purity of 20 dB optimized in comparison to the existing designs. Bo Zhou, Kun Zhang, Wenbiao Zhou, Yanjun Zhang, and Dake Liu Copyright © 2013 Bo Zhou et al. All rights reserved. Optimized Hyper Beamforming of Linear Antenna Arrays Using Collective Animal Behaviour Mon, 22 Jul 2013 10:22:45 +0000 http://www.hindawi.com/journals/tswj/2013/982017/ A novel optimization technique which is developed on mimicking the collective animal behaviour (CAB) is applied for the optimal design of hyper beamforming of linear antenna arrays. Hyper beamforming is based on sum and difference beam patterns of the array, each raised to the power of a hyperbeam exponent parameter. The optimized hyperbeam is achieved by optimization of current excitation weights and uniform interelement spacing. As compared to conventional hyper beamforming of linear antenna array, real coded genetic algorithm (RGA), particle swarm optimization (PSO), and differential evolution (DE) applied to the hyper beam of the same array can achieve reduction in sidelobe level (SLL) and same or less first null beam width (FNBW), keeping the same value of hyperbeam exponent. Again, further reductions of sidelobe level (SLL) and first null beam width (FNBW) have been achieved by the proposed collective animal behaviour (CAB) algorithm. CAB finds near global optimal solution unlike RGA, PSO, and DE in the present problem. The above comparative optimization is illustrated through 10-, 14-, and 20-element linear antenna arrays to establish the optimization efficacy of CAB. Gopi Ram, Durbadal Mandal, Rajib Kar, and Sakti Prasad Ghoshal Copyright © 2013 Gopi Ram et al. All rights reserved. Efficient and Accurate Optimal Linear Phase FIR Filter Design Using Opposition-Based Harmony Search Algorithm Mon, 10 Jun 2013 08:20:04 +0000 http://www.hindawi.com/journals/tswj/2013/320489/ In this paper, opposition-based harmony search has been applied for the optimal design of linear phase FIR filters. RGA, PSO, and DE have also been adopted for the sake of comparison. The original harmony search algorithm is chosen as the parent one, and opposition-based approach is applied. During the initialization, randomly generated population of solutions is chosen, opposite solutions are also considered, and the fitter one is selected as a priori guess. In harmony memory, each such solution passes through memory consideration rule, pitch adjustment rule, and then opposition-based reinitialization generation jumping, which gives the optimum result corresponding to the least error fitness in multidimensional search space of FIR filter design. Incorporation of different control parameters in the basic HS algorithm results in the balancing of exploration and exploitation of search space. Low pass, high pass, band pass, and band stop FIR filters are designed with the proposed OHS and other aforementioned algorithms individually for comparative optimization performance. A comparison of simulation results reveals the optimization efficacy of the OHS over the other optimization techniques for the solution of the multimodal, nondifferentiable, nonlinear, and constrained FIR filter design problems. S. K. Saha, R. Dutta, R. Choudhury, R. Kar, D. Mandal, and S. P. Ghoshal Copyright © 2013 S. K. Saha et al. All rights reserved. PSO Based PI Controller Design for a Solar Charger System Mon, 13 May 2013 15:19:38 +0000 http://www.hindawi.com/journals/tswj/2013/815280/ Due to global energy crisis and severe environmental pollution, the photovoltaic (PV) system has become one of the most important renewable energy sources. Many previous studies on solar charger integrated system only focus on load charge control or switching Maximum Power Point Tracking (MPPT) and charge control modes. This study used two-stage system, which allows the overall portable solar energy charging system to implement MPPT and optimal charge control of Li-ion battery simultaneously. First, this study designs a DC/DC boost converter of solar power generation, which uses variable step size incremental conductance method (VSINC) to enable the solar cell to track the maximum power point at any time. The voltage was exported from the DC/DC boost converter to the DC/DC buck converter, so that the voltage dropped to proper voltage for charging the battery. The charging system uses constant current/constant voltage (CC/CV) method to charge the lithium battery. In order to obtain the optimum PI charge controller parameters, this study used intelligent algorithm to determine the optimum parameters. According to the simulation and experimental results, the control parameters resulted from PSO have better performance than genetic algorithms (GAs). Her-Terng Yau, Chih-Jer Lin, and Qin-Cheng Liang Copyright © 2013 Her-Terng Yau et al. All rights reserved. A High Voltage Ratio and Low Ripple Interleaved DC-DC Converter for Fuel Cell Applications Sun, 23 Dec 2012 16:23:56 +0000 http://www.hindawi.com/journals/tswj/2012/896508/ This paper proposes a high voltage ratio and low ripple interleaved boost DC-DC converter, which can be used to reduce the output voltage ripple. This converter transfers the low DC voltage of fuel cell to high DC voltage in DC link. The structure of the converter is parallel with two voltage-doubler boost converters by interleaving their output voltages to reduce the voltage ripple ratio. Besides, it can lower the current stress for the switches and inductors in the system. First, the PSIM software was used to establish a proton exchange membrane fuel cell and a converter circuit model. The simulated and measured results of the fuel cell output characteristic curve are made to verify the correctness of the established simulation model. In addition, some experimental results are made to validate the effectiveness in improving output voltage ripple of the proposed high voltage ratio interleaved boost DC-DC converters. Long-Yi Chang, Kuei-Hsiang Chao, and Tsang-Chih Chang Copyright © 2012 Long-Yi Chang et al. All rights reserved.