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VLSI Design
Volume 5 (1996), Issue 1, Pages 89-100
http://dx.doi.org/10.1155/1996/23706

Zener Zap Anti-Fuse Trim in VLSI Circuits

Brigham Young University, Provo 84602, UT, USA

Received 23 October 1994; Accepted 10 April 1995

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents an overview of Zener zap anti-fuse trim as used to achieve improved accuracy in precision integrated circuits. Because this technology spans design and manufacturing, elements of design, layout, processing, and testing are included. The mechanism is defined and typical applications are discussed. Layout considerations of anti-fuse devices are summarized and complex trim networks and multiplexed control methods are presented. Both bipolar and CMOS process implementations are considered. The paper also contains a bibliography which includes U.S. patents, which make up a large part of the technical documentation of this technology.