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VLSI Design
Volume 4 (1996), Issue 2, Pages 141-147
http://dx.doi.org/10.1155/1996/63890

Hardware Design Rule Checker Using a CAM Architecture

1Department of Electrical and Computer Engineering, The State University of New York at Buffalo, Buffalo 14260, NY, USA
2135 Bell Hall, Department of Electrical and Computer Engineering, The State University of New York at Buffalo, Buffalo 14260, NY, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a hardware implementation of design rule checker using a specialized Content Addressable Memory(CAM) for the Manhattan geometric designs. Two dimensional relationships between rectangular objects in a design are checked with one dimensional design rules. The input data is processed by the pixel pre-processor in such a way that direct comparison between the input data and the stored rules in the CAM is possible. The comparison by the CAM reduces the number of memory references and logic operations of pattern matching and the simple architecture of the system enables a low cost implementation.