I_DDQ Testing Experiments for Various CMOS Logic Design Structures

Abstract

In this paper, we present two studies. The first study constitutes an assessment of the effectiveness of I_DDQ (quiescent power supply current) in detecting transistor-level defects for three CMOS logic design styles. This study was carded out by designing, simulating, fabricating, and testing CMOS devices with built-in defects. The second study involves an assessment of I_DDQ in a production-type environment and the effect of bum-in on I_DDQ levels. This study was carried out in a production facility. The results show that I_DDQ testing can detect some types of defects in precharge and pseudo-NMOS circuits but may require partitioning circuitry for the latter.