Operational and Test Performance in the Presence of
Built-in Current Sensors

doi:10.1155/1997/54757

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VLSI Design
Volume 5 (1997), Issue 3, Pages 285-298
doi:10.1155/1997/54757

Operational and Test Performance in the Presence of Built-in Current Sensors

Sankaran M. Menon,¹ Yashwant K. Malaiya,² Anura P. Jayasumana,³ and Carol Q. Tong⁴

¹Dept. of Electrical and Chemical Engineering, South Dakota School of Mines & Technology, 501, E. St. Joseph St., Rapid City 57701, SD, USA
²Dept. of Computer Science, Colorado State University, Fort Collins 80523, CO, USA
³Dept. of Electrical Engineering, Colorado State University, Fort Collins 80523, CO, USA
⁴SUNRISE Test Systems, Inc., 47211 Lakeview Blvd., Fremont 94538-6530, CA, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The effects of Built-In Current Sensors (BICS) on IDDQ measurements as well as on the performance of the circuit under test are considered. Most of the Built-In Current Sensor designs transform the ground terminal of the circuit under test into a virtual ground. This causes increases in both propagation delay and IDDQ sampling time with the increase in the number of gates, affecting both test as well as operational performance. The effects that current sensors have on the operational and test performance of a circuit are considered. Circuit partitioning may be used for overcoming the effects of BICS on IDDQ measurements as well as on the performance of the circuit under test.