VLSI Design 
Volume 7 (1998), Issue 1, Pages 97-110
doi:10.1155/1998/38483

Placement and Routing for Performance-Oriented FPGA Layout

Michael J. Alexander,1 James P. Cohoon,2 Joseph L. Ganley,3 and Gabriel Robins2

1School of Electrical Engineering and Computer Science, Washington State University, Pullman 99164-2752, WA, USA
2Department of Computer Science, University of Virginia, Charlottesville 22903-2442, VA, USA
3Cadence Design Systems, lnc., San Jose 95134-1937, CA, USA

Abstract

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.