Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

Das, Sunil R.; Goel, Nita; Jone, Wen B.; Nayak, Amiya R.

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VLSI Design
Volume 7 (1998), Issue 2, Pages 191-201
doi:10.1155/1998/45472

Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

Sunil R. Das,^1,2 Nita Goel,² Wen B. Jone,³ and Amiya R. Nayak⁴

¹Presently with Dept. of Electrical Engineering and Computer Sciences, Computer Science Division, University of California, Berkeley 94720, CA, USA
²Dept. of Electrical Engineering, Faculty of Engineering, University of Ottawa, Ottawa KIN 6N5, Ontario, Canada
³Dept. of Computer Science and Information Engineering, National Chung Cheng University, Taiwan, Chiayi 62107, China
⁴School of Computer Science, Carleton University, Ottawa KIS 5B6, Ontario, Canada

Received 10 June 1997

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In this paper, we focus on the use of signature-based output compaction technique for built-in self-testing of VLSI circuits. We give algorithm for single-output and multiple-output signature generation using exhaustive test patterns extending the syndrome conccpt. The signature wc develop is a functional signature and is very effective for both input and internal line fault detection, as seen from simulation on various benchmark circuits. The signature generators can bc easily implemented using the current VLSI technology.