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VLSI Design
Volume 7 (1998), Issue 1, Pages 59-72
http://dx.doi.org/10.1155/1998/76525

Power Distribution Synthesis for VLSI

Department of Electrical and Computer Engineering, University of California, Santa Barbara 93106, USA

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The synthesis of the power distribution network is an important problem in the layout design of VLSI systems. In this paper we propose novel methods to solve the problem of designing minimal area power distribution nets, while satisfying voltage drop and electromigration constraints. We will see that our methods significantly improve upon current techniques. We propose two novel greedy heuristics for power net design-one based on bottom-up tree construction using greedy merging and the other based on top-down linearly separable partitioning. We test the efficacy of our techniques on benchmark instances. The areas required by our methods on typical instances are significantly smaller than those obtained using previous methods.