About this Journal Submit a Manuscript Table of Contents
VLSI Design
Volume 7 (1998), Issue 1, Pages 85-95
http://dx.doi.org/10.1155/1998/81296

Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

1Dept. of Computer Engineering, Hannam University, Taejon 306-791, Korea
2Dept. of Computer Engineering, Seoul National University, Seoul 151-742, Korea

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridded channel routing. The proposed technique is compared with previous track-oriented techniques, especially a track permutation technique whose performance is bounded by an exhaustive track permutation algorithm. Experiments showed that the presented technique is more effective than the track permutation technique.