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VLSI Design
Volume 10 (1999), Issue 1, Pages 1-20
doi:10.1155/1999/81698

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

Dirk Stroobandt and Jan Van Campenhout

University of Ghent, Department of Electronics and Information Systems, St.-Pietersnieuwstraat 41, Gent B-9000, Belgium

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor δ ≈ 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.