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VLSI Design
Volume 10 (1999), Issue 1, Pages 35-55
http://dx.doi.org/10.1155/1999/85272

Logic Synthesis for a Regular Layout

1Electrical and Computer Engineering Department, Portland State University, 1800 6th Avenue, Portland 97207-0751, OR, USA
2Lattice Semiconductor Corporation, 5555 NE Moore Count, Hillsboro 97124-0118, OR, USA

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.