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VLSI Design
Volume 10 (2000), Issue 3, Pages 265-279
http://dx.doi.org/10.1155/2000/28323

Reconfigurable Architectures for System Level Applications of Adaptive Computing

University of Southern California, Information Sciences Institute, 4350 N. Fairfax Drive, Suite 770, Arlington 22203, VA, USA

Received 1 February 1999; Accepted 1 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a highspeed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created. The Research Reference Platform (RRP) is a MyrinetTM cluster of PCs with PCI-based FPGA accelerators (SLAAC-1). The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPCTM nodes with VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad- PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for successful ACS technology insertions is source-code compatibility between the RRP and DRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2 accelerators and how the network-centric SLAAC system-level architecture has shaped their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.