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VLSI Design
Volume 11 (2000), Issue 1, Pages 59-74
http://dx.doi.org/10.1155/2000/92954

Optimal Detector Design for On-line Testing of Linear Analog Systems

TIMA-Laboratory, 46, Av. Félix Viallet, Grenoble F-38031, France

Received 1 April 1999; Accepted 5 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The design of integrated fault detector for on-line testing of linear analog systems is discussed in this paper. The method consists in a concurrent processing of available the node voltage signals to provide a residual on-line, that carries information about the faults. Contrary to the few previous works dealing with the particular case of state variable analog systems, the method proposed here is useable without limitation for a larger class of linear analog systems, even when the state variables are not available as measurable voltages. For this purpose, an algorithm providing an extended state space model for any linear analog system from its netlist description is developed and implemented.