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VLSI Design
Volume 12 (2001), Issue 2, Pages 139-150
http://dx.doi.org/10.1155/2001/23925

Power-conscious Scheduling for Real-time Embedded Systems Design

1Center for Collaborative Research and Institute of Industrial Science, University of Tokyo, Tokyo 106-8558, Japan
2School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, South Korea

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.