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VLSI Design
Volume 12 (2001), Issue 3, Pages 449-455
http://dx.doi.org/10.1155/2001/25179

Simultaneous Switching Noise Minimization Technique Using Dual Layer Power Line Mutual Inductors

VLSI Design Lab., Dept. of Electronic Engineering, Hallym University, Chunchon 200-702, South Korea

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A novel technique for minimization of simultaneous switching noise is presented. Dual Layer Power Line (DLPL) structure is newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is halfdivided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly minimize the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.