About this Journal Submit a Manuscript Table of Contents
VLSI Design
Volume 12 (2001), Issue 2, Pages 125-138
http://dx.doi.org/10.1155/2001/65638

Power Optimization of Delay Constrained Circuits

1#L458, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA
2#L463, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA
3#L469, Technological Institute, 2145 Sheridan Road, Evanston, IL 60208, USA

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.